THE COMMON PLATFORM alliance, Global Foundries, IBM and Samsung had a conference Tuesday to announce their renewed alliance and show off their respective wares. Samsung’s NS Woo, President and GM of the LSI Division kicked it off in the first of three keynotes.
Each partner outlined a different aspect of their alliance; Samsung talked about the upcoming challenges they face, basically why there was a need for an alliance, and where the future growth would come from. Then Global Foundries covered manufacturing challenges, and IBM followed with a deep dive into the future and far future tech that the alliance is working on in the dark catacombs under Fishkill.
Everyone agrees that the future growth prospects for silicon are going to be phones, more specifically smartphones, and the cutting edge silicon they demand. If a foundry wants a piece of that pie, they had better have a well sorted low power (LP) process, and almost as importantly, a chip stacking, assembly, and packaging arsenal. They also have to work together to make a, well, common platform, something the big customers are now demanding.
Doing all of this is expensive, extremely expensive, so expensive that the number of companies that are trying to do it on the 32/28nm node is only 7. Most of those are teaming up into alliances to share the burden, risk, and cost. That is the first aspect of the common platform.
How expensive is it? Mr Woo was saying the 20nm process cost about $1.4 Billion to develop, and that is not counting the cost of a fab. On the upcoming nodes, building a fab will run in the high single digit billions of dollars, not a trivial thing for any company.
With an alliance like Common Platform, customers who spend tens of millions of dollars or more, several years, and sometimes bet their company on a single chip tend to feel reassured about the manufacturing side of things. Trivial as this may sound, ask yourself how many millions of dollars and how many years you would commit to a partner that may not hold up their side of things?
Back to the power side, the main weapon there is now High-K/Metal Gate (HKMG) transistors. Intel has been shipping them since their 45nm process debuted about three years ago, but the Common Platform guys look to be second with TSMC a very close third.
HKMG basically lowers leakage by a huge degree, 10x is doable, or you can take the power savings as performance if your chip is not power bound. If you can make them, HKMG transistors are a clear win. Leakage gets so bad below 45/40nm that smaller geometries are basically not a sane prospect with older transistor materials.
That brings up the next big problem, making the little buggers. Intel has shown it can be done on 45nm, and again at 32nm with an updated stack. Sources tell SemiAccurate that the biggest hurdle for HKMG 32nm SOI manufacturing was passed late last year and things are looking up for a Q2 Llano introduction. Sources also describe the 28nm gate stack as ‘substantially similar’ to 32nm, so things are looking up for that node.
Related to the question of ‘can they?’ is ‘how do they?’, basically gate first vs gate last manufacturing. The short version of the debate is that gate first is much denser than gate last, a 2x shrink vs a 1.6x shrink, but has notably lower yields. How much lower is a trade secret, but it isn’t hard to do the math and come up with a number of less than 20% lower. If it was more than 20% lower, the math says that the same chip would be cheaper to make on gate last. The end result performs about the same either way.
There are a lot of other factors like design rules and other somewhat indirect costs. With the numbers crunched, the Common Platform agreed to do gate first on 32/28nm, and now is admitting that they will switch to gate last on the next node, 22/20nm. Intel has been doing gate last from day one, TSMC did a late-game switch a while ago, ending up with gate last as well. There seems to be a pattern here.
Behind the scenes, we are told this was nothing less than an acrimonious and bitter debate, with IBM coming down on the gate first side, Samsung and GloFo wanting gate last. IBM won this round, Samsung and GloFo the next. Who knows what 14nm will bring?
Samsung also talked about packaging technologies, specifically 3D integration with flip-chip package on package (FC-PoP) and laser drilled package on package (LDP-PoP). Samsung claims the full LDP-PoP use will drop package area by 33% and height by 13%. When you add embedded passive components to a FC-POP package, then use a metal core PCB, you can gain 20% more performance from each technology, but performance in what regard was not specified.
The next step, through Silicon Vias (TSVs) is near but not here yet. Basically this is chip stacking by drilling holes in the die, and putting a wire through it to pass signals. You then line up the dies, bond them, and hope it works. Some of the problems here have been solved, others are a bit farther off. Intel seems to be leading the charge to advanced packaging, but the Common Platform guys are not far behind.
One heavily talked about benefit of stacking, whether through TSVs or other methods, is the potential for wide I/O. As Intel is going to show off soon, if you put a memory chip on a device and use silicon scale interconnects, you can up the width of the connections by an order of magnitude. This will dramatically speed up DRAM bandwidths, but won’t do much for latency. It is a game changer.
In the end, the Mr Woo did a very good job of outlining why the Common Platform alliance is needed, and talked a bit about what problems they are solving. It was a broad brush used to show customers and partners that they are in good hands, and future plans are being executed on. How they are being executed on, and what the next steps are were covered by the next two speakers.S|A
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