Will Sandy-E ship without PCIe3?

Rumors point to borked PHYs and multi-layer respins

Intel logo 63x58 Will Sandy E ship without PCIe3?The problems with Intel’s (NASDAQ:INTC) Sandy Bridge-E have finally started to come in to focus, and they are troubling. We mentioned several potential issues that could be causing the delay earlier, and the answer is looking like they were all involved but lead back to one problem.

Several sources told SemiAccurate that Sandy-E was having problems with PCIe3, some others said it was a chipset communications problem, and yet more mentioned multi-CPUs. We rounded up all the rumors, and looked at how each of them could be at fault here. It looks like the culprit is the PCIe3 PHYs, they are borked.

Intel has gone to ‘DMI/CSI/MarketingPablum’ for their interconnect between CPUs and between a CPU and a chipset. It works quite well, but it isn’t all that much of a big deal on the physical side. The DMI/CSI/MP link is simply a PCIe physical layer with proprietary overlays, encrypted in newer flavors, and questionably patented to keep others away. The idea is simple, keep the wires coming off the CPU to the same voltages, same frequencies, and simplify things as much as possible. This is a really good idea.

Well, it would be unless you have a problem in the common circuitry, in which case it all goes pear shaped in a hurry. Sources deep within the industry tell us that the problem is that the PHYs for the PCIe3 side, i.e. the 8Gbps ones are screwed up badly enough that it requires at least a multi-layer respin, if not a base layer respin. This in turn takes down PCIe3, chipset communications, and anything else that may be using those blocks, like the chipset connection.

Those same sources tell us that the PHYs run just peachy at PCIe2 speeds, so no problem there. This will probably mean that the Sandy-E parts that come out in WW46 (some say 11/11/11, but that is probably not the real date) will be neutered to PCIe2. When the fixed parts come out in Q1, they will of course be shunted to the server side first, and then to the consumer side.

How this is going to be spun is going to be fun to watch. Will Intel release an eXXXtreme edition iSomethingmeaningless with PCIe3 and fuse it off for most of the line? Will they up the model numbers by a yet more meaningless amount to make new buyers think they are getting something more than a bug fix? Will they just slipstream things in quietly? Who knows, but I would definitely wait for a solid explanation before putting your money down, Sandy-E is going to be really fast, but it isn’t going to be really cheap.

That brings us to the more troubling question, this is the second high speed PHY that Intel seems to have botched in recent months. The last one was the was for the Sandy Bridge SATA3 bug, but that had a ‘miracle fix’. Why no <1 month turn around this time? Could it be that the explanation given by the company last time was… ummm…. farcical? If you ask OEMs about when they talked to Intel about the problem, it pokes so many holes in the story that it makes you wonder, but who are we to question official doctrine? Still, you have to wonder.S|A

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 Will Sandy E ship without PCIe3?

Charlie Demerjian

Roving engine of chaos and snide remarks at SemiAccurate
Charlie Demerjian is the founder of Stone Arch Networking Services and SemiAccurate.com. SemiAccurate.com is a technology news site; addressing hardware design, software selection, customization, securing and maintenance, with over one million views per month. He is a technologist and analyst specializing in semiconductors, system and network architecture. As head writer of SemiAccurate.com, he regularly advises writers, analysts, and industry executives on technical matters and long lead industry trends. Charlie is also a council member with Gerson Lehman Group.