The two siblings are said to be GK104-400 and GK104-335, basically a full working and partially fused off version of the same chip. The -400 is said to be an “8 group” device, the -335 described as “7 group’. If you recall the sad tale of Fermi/GF100, the chip had large swathes of shaders turned off, the ability to do less radical surgery was not there. This is a fairly painful way to deal with defects, the more granular you can make the disabling, the better off you are.
Nothing comes for free in the silicon world, and the art of chip design is balancing granularity with cost. Nvidia botched this badly in Fermi, and paid a high price. The only good that came of it was the entertainment in seeing their spokespeople spin ever increasing leaps of logic in public. This however doesn’t placate investors much, even if they do smile.
With this new description of the -400 and -335 variant of GK104, it looks like Nvidia has implemented what AMD has been doing since at least the R700 (HD4000) chips, if not earlier. Instead of being forced to fuse off large blocks of shaders as a minimum, it looks like they can now do much smaller chunks. In Fermi terms, instead of taking a CU at a whack, they can now do portions of a CU too.
This should greatly improve yields, allow for endless SKU variations, and generally make things better. Of course, it comes at a die size penalty, but after the last learning experience, it would be foolish to do otherwise.S|A
Latest posts by Charlie Demerjian (see all)
- Broadcom’s Quartz implements Time Sensitive Network Ethernet - Apr 19, 2017
- Intel mercy kills IDF - Apr 17, 2017
- Is Intel’s Hyperscaling really a change? - Apr 4, 2017
- Intel crosses an unacceptable ethical line - Mar 27, 2017
- Intel releases consumer M.2 Xpoint SSDs - Mar 27, 2017