We first told you about these chips in 2010, and now the names have a bit more clarity as the FPGAs inch their way closer to availablility. These two families of Speedster22i, the HD (High Density) and HP (High Performance), both integrate hard I/O logic on the chip. HD comes in four flavors, HP is not specified, but all are made on Intel’s 22nm process.
HD has up to 1.7 million LUTs, 144Mb (my guess is that would be 16GB of parity enabled memory, not 18 Mb of non-parity), and a staggering number of high speed SerDes. How staggering? 16 * 28Gbps AND 64 12.75Gbps AND 960 2.133Gbps general I/Os. This is more than enough to not only emulate a Hayes 1200 in real time, but likely has enough free cycles to emulate a Hayes 300 on the same chip too!
Moving on to the HP family, Achronix claims that the self-timed FPGA can operate at 1.5Ghz, quite fast for an FPGA. Interestingly though, the HD family is not mentioned as being self-timed, something that Achronix is known for. The largest HD chip has 250K LUTs and 64Mb of memory on die.
Neither chip has a shipping date, today’s announcement is just a glorified “call us for more info, we will pick up the phone now” piece. Tools to make something on both parts are available now, but you will have to wait a bit for physical parts to play with, and a bit longer for volume. That said, they will still probably be the first 22nm FPGA on the market.S|A
Latest posts by Charlie Demerjian (see all)
- Intel releases INDE cross-everything dev tools - Oct 16, 2014
- Another Google silicon project comes to light - Oct 15, 2014
- Tyan launches an OpenPower Power 8 reference design - Oct 9, 2014
- SemiAccurate gets word of the first Google silicon - Oct 6, 2014
- ARM releases mbed Device Server IoT software - Oct 1, 2014