The last few times we wrote about Penwell, Medfield, and other Intel 32nm Atom phone chips, you might have noticed the diagrams. Or lack thereof. Intel didn’t want us to use any of their presentations so we didn’t, but now we can.
During Hot Chips 24 earlier this year, Intel put on a presentation about the Penwell SoC, and there were a few juicy new bits here and there. Better yet, there were no restrictions on the diagrams, so we can actually illustrate the new bits too. It might be worth reading the older ones, this and this if you don’t already know the SoC well, I am not going to go over the basics again, just fill in a few blanks.
First some hard specs. All comparisons are between the Medfield reference platform and the Moorestown version that preceded it. The board is much smaller in this new generation, 4150mm^2 vs 5000mm^2 previously, a 17% drop. Standby power goes down by almost twice that, 14mW vs 21mW is a 33% decrease, and browsing power drops a by almost as much, 1.2W to .85W a 29% decrease. Of the three, board space is probably going to give Intel the biggest gain with carriers, the other two were not all that out of line with contemporary ARM SoCs.
Board diagram for an Intel reference phone
As you can see, the board is shaped a little oddly compared to, well, almost any other PCB out there, but it does provide a nice spot for a battery. That said, a smaller square board seems to make a lot more sense, and could possibly shave even more area off the tally. The diagram above does do a good job of explaining how complex a modern phone PCB is, this is not a 386 class motherboard.
The Medfield package diagram
Above is the diagram and picture we could not show you earlier, the PoP SoC setup that Intel has devised for Penwell. Notice how it it is a normal PCB with a second PCB on top as a spacer. Mounted on top of that is a third PCB that the system memory is placed on. As the diagram says, OEMs can mount up to 2GB of LPDDR2 to this board, but cost and power use will likely keep that number down in practice. This stacking for memory is probably one of the main reasons why the system board shrunk, no memory, no traces to memory, and everything in the vertical plane is the key.
The die shot at last
Not much to say about this one, it just gives you a blurred out die shot with a diagram. That said, it gives you a good idea of what blocks take up what space, and the relative transistor budgets. If you look at the size of the GPU compared to the other blocks, you can understand why Intel is not winning many 3D benchmarks. The camera block takes up almost the same space as the GPU, and the video engine is pretty close too.
Power on a curve
Last up, we have the power use curve. It is pretty standard, not to mention simplified, but being laid out like this gives you a pretty good idea why the whole HUGS (Hurry Up and Go to Sleep) concept is useful. Pick your points on the curve right and you can minimize power use for any given application. This chart leaves a lot to be desired for markings, but it gets the point across well. Speed up, get the job done, then drop to as deep an idle as possible. Every chip does it now, and this chart doesn’t just tell you why, it shows you.
In the end we have a few good points, nothing earth-shattering, just things we were not able to bring you before. Hopefully the 22nm parts will not have the same lag, but no promises. Can anyone image what would have happened if Nokia hadn’t jumped off this burning platform? No, don’t answer that.S|A
Latest posts by Charlie Demerjian (see all)
- Imagination outs a lot of details and demos at CES - Jan 23, 2015
- And the name of Qualcomm’s 64-bit post-Krait core is….. - Jan 21, 2015
- Goodway shows off the first USB-C hub we’ve seen - Jan 21, 2015
- The ongoing twists to the Nvidia patent trolling ‘Kepler license’ scheme - Jan 20, 2015
- Adata has some evolutionary toys plus a few twists - Jan 19, 2015