IBM had two packaging goodies on display at Common Platform including one that SemiAccurate has shown you before. One was a 2.5D packaging vehicle with vias and an interposer, the other was a full 3D eDRAM stack with vias, not wire bonding.
If you recall the chips we showed you last year under the Power 7+ name, they were there again, or at least something very similar to those chips were at Common Platform this year. Once again, it didn’t have anything to call out what the chip was exactly, but we were told it was a “2.5D TSV test vehicle” this time around, but no more. So a little more construction, a little less logic info this time around, win some, lose some.
Next up was a new one, and while similar to the little package shown last year, it was said to be all new. The problem with unlabeled parts is that they all look the same, blackish rectangles on green squares. In a bit of a change of pace, IBM showed a device that looked, err, just like that description, at least the one without the lid did.
32nm 3D stacked eDRAM
The nice person setting up the IBM booth at Common Platform described this one as a “32nm Heterogenous 3D stack of eDRAMs”. When asked how the stacking was done, our initial thoughts about vias were confirmed. I wonder what upcoming devices that IBM could be in the running to manufacture could use this technology? I guess we will never know for sure.
In the end, knowing exactly what these devices are shows that IBM is deadly serious about making 2.5D and 3D structures. They can make active interposers, full 3D heterogeneous stacks, 2.5D stacks, and likely different combinations of the above technologies. Stacking has been demonstrated on organic and ceramic packages with both lidded and unlidded final devices and interposers up to 50mm on a side whispered in our ear. That about covers the big bullet points, what more do you want for your next project?S|A
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