Samsung is talking a bit about their upcoming 14nm FinFET process, and they cleared up a few grey areas about the hybrid nature of this process. During a talk with Samsung’s Ana Hunter late last week, much of the confusion about what they are doing was cleared up.
You might recall that after the Common Platform conference in January, the three partners revealed that their 14nm process would use FinFETs in combination with the interconnects from the previous generation 20nm process. The official word from all three partners, Samsung, IBM, and Global Foundries was that this hybrid tech speeds time to market, lowers design costs, and still brings customers the benefits of FinFETs.
Detractors would then chime in that it was obvious the three couldn’t do a ‘real’ 14nm shrink so they had no other choice. They also said that there would be no shrink because the die size is determined by the interconnects more than anything else. Based on the information that was revealed at the time this seemed to be the case, but there was little public information to go on.
Who is right? The 14nm FinFETs would deliver the low leakage characteristics the industry needs, that is almost a given. On top of this the design times should be lower, much of the 20nm learning could be carried over as can many of the design tools. To what degree this is true still remains to be seen but there is nothing inherently problematic about the claims from the Common Platform foundries. The speed benefits should also mostly be there as well but the shrinkage, or lack thereof, was a big red flag to even the most casual observers.
Luckily for us, Ana Hunter of Samsung cleared up a lot of the issues that were floating around the Samsung version of the process. Please bear in mind that although the bulk of the technology is the same between the three partners, all can and likely will deliver different flavors of 14nm to their customers. What Samsung is doing may or may not be mirrored by IBM and Global Foundries, and vice versa.
The first thing is that Samsung is on track to deliver the process on the promised schedule, that would be 14nm customer tapeouts in Q1/2014. This is a pretty good validation that the time to market advantages of changing the transistors and not the interconnects is happening as promised. At the moment Samsung just completed the third rev of their Process Design Kit (PDK) and are using them internally for logic development. Customers have 14nm test wafers running through the fabs right now too, the main goal is to run test chips to see what types of structures will best suit their planned chips and how aggressively they will implement some of the offered technologies. Samsung described the yields on current test chips as good and logic libraries are well in to development now.
For the 14nm process the Front End of Line (FEOL) is completely new, the Back End of Line (BEOL) is mostly carried over from 20nm. Metal 1 and higher are the same as the older 20nm process so any characteristics determined by that technology will be constant for all three partners. Samsung is modifying the playbook from there a bit by focusing on tighter poly and contact pitches. There are no new design rules but Samsung is being fairly aggressive in pushing these two areas and likely a few more not discussed too.
The refrain in January was that 14nm would bring no die shrinks, but that isn’t quite the case at Samsung. While it is true that the 50% shrinks of processes past are not going to happen this time, there will be between a 7% and 15% shrink thanks to the poly and contact pitch work. This has been validated by SRAM test parts, they are showing those gains and they are fairly representative of what you can get out of a device.
Much of what the customers are doing with the test chips being run at the moment centers around how aggressively they want to push these boundaries for their devices. If they want to take full advantage of what Samsung is doing the maximum 15% should be achievable but works is still ongoing. How much each partner chooses to push shrinks will likely be the main differentiator between Samsung, IBM, and Global Foundries.
In the end you will get a chip that looks like it was built on a 20nm process, is sized like it was built on a 20nm process, but has the dynamic range and power consumption of a 14nm chip. You can also order wafers built on the process much sooner than you could a full 14nm process, and reuse much of what you did to build the 20nm variants of your chips. Cost will obviously go up, it always does, but to what degree is still an open question, one unlikely to be publicly answered by any of the players in the near future.
The one question that remains open is what to call this process. All of those offering it stick to the 14nm script but their competition insists that it is 20nm, the rest is spin. SemiAccurate sees both of their points and both are quite valid. The performance is 14nm, the size is 20nm, and there is nothing like it in the past to compare to. So what do you call it? Because there won’t be a full 14nm FEOL + 14nm BEOL process coming from any of the three partners. We will call it 14nm to avoid confusion but won’t argue that it could also correctly be called an enhanced 20nm process.S|A
Latest posts by Charlie Demerjian (see all)
- A new body of water forms near Intel - May 27, 2015
- Another Intel memory code name pops up - May 20, 2015
- AMD finally talks about HBM memory - May 19, 2015
- Disco makes hexagonal and non-regular chips possible - May 18, 2015
- Qualcomm refreshes it’s IoT device lines - May 14, 2015