Everspin and Northwest Logic have teamed up on and FPGA based DDR3 controller supporting ST-MRAM. If you were looking for an easy way to prototype and ST-MRAM based device, your job has been made a lot simpler.
You may recall that Everspin’s ST-MRAM implements DDR3 memory protocols with a few key differences. Those are persistence, ST-MRAM doesn’t lose its state when powered down, and a few minor timing differences here and there. In short you can use it just like DDR3 for the most part with some minor changes, essentially lookup tables for timing and a few more procedures to deal with persistence and clearing memory when needed.
Today’s big news is that the Northwest Logic DDR3 memory controller IP that can support Everspin ST-MRAM now comes in Xilinx Virtex-7 form. No this is not a way to save on shipping the IP in paper format, it is done and tested on the Virtex-7 so you can just implement the rest of your design and not worry about the memory. While the memory controller is not new, the ease at which you can implement it is. Because of the minor changes needed to support ST-MRAM, the controllers should not take up many more gates than a normal DDR3 controller.
While talking to Everspin about the new controller IP implementation, a few interesting bits came up that we thought you might enjoy. First is that the 90nm process that the current devices are built on is not quite a 90nm process. The base transistor layer (FEOL) is indeed 90nm but the MTJ (Magnetic Tunneling Junction) layer on top of that is built on an undisclosed but more aggressive geometry.
Since it is a 1T:1MTJ device, you can guess that the process choice was done to keep the ratio between the devices the same to not waste wafer space. More interesting is how things are done, the transistors are built at an external foundry then the wafers are shipped to Everspin’s palatial island headquarters (Note: Not really on the palatial or island parts, we just thought it was funny) to add the MTJ layers and the metals on top of them. It is not just a multi-step process, it a multi-location process too, quite unusual.
Next is the team-up with Globalfoundries on 40nm and 28nm, possibly more too, processes. Since ST-MRAM cell size shrinks with transistors, going from 90nm to 28nm is four shrinks, that would put the current 64Mb devices at 512Mb on the announced nodes. Since GF has 20nm and 14nm on deck, you might expect Everspin to have 1Gb and 2Gb ST-MRAMs in process for those nodes. They won’t comment any farther than 28nm though, but don’t be surprised by an announcement one day.
The current Everspin devices are built on 200mm wafers, GF will be building them on 300mm silicon so expect prices to fall quite a bit for higher density chips. This hopefully is enough to kick off a virtuous volume and price cycle, at least we hope it does. In any case Everspin does not anticipate these new nodes will need a more aggressive pitch on the MTJ layer, it should be fairly straightforward from here on out.
So in the end there isn’t much astounding new news. The current Northwest Logic DDR3 + ST-MRAM controller IP is now implemented on a Xilinx Virtex-7 FPGA for ease of implementation. That will make the engineers happy. The rest is more or less geek trivia that the non-MRAM implementers out there will find useful during forum debates. Enjoy.S|A
Latest posts by Charlie Demerjian (see all)
- AMD talks about Vega at a high level - Jan 17, 2017
- Intel unleashes more Kaby Lake SKUs on the yearning public - Jan 4, 2017
- Qualcomm opens up a bit more on the 10nm Snapdragon 835 SoC - Jan 3, 2017
- AMD’s Freesync 2 changes the display game - Jan 3, 2017
- Coffee Lake points to issues with Intel’s 10nm process - Dec 28, 2016