Last week AppliedMicro (APM) and the Linley Group released a white paper detailing the performance goals of APM’s X-Gene 3 server chips that are due for release in H2 2017. In this white paper it becomes clear that APM believes that their 32 core ARMv8 server chip will be competitive with Intel’s current Broadwell-based Xeon E5 chips. These performance goals are based largely on the SPECint_rate2006 benchmark where APM is projecting X-Gene 3 to pull of a total score of 550 with lower but similar per thread performance compared to Intel’s Xeons. Of course these numbers are highly speculative and based on APM’s internal modeling of the X-Gene 3’s custom core architecture running a slice of the SPECInt_rate2006 benchmark using FPGA emulation.
Despite the squishyness of this information the Linely Group’s white paper reveals a lot of details about X-Gene 3 and its successor the X-Gene 3XL. Starting with the high-level configuration of the X-Gene 3 which will offer 32 custom 64-bit CPU cores, 8 DDR4 memory channels with speeds of up to DDR4-2667, clock-speeds of 3 Ghz, 256KB of L2 cache per core, 32MBs of L3 cache, and a revised fabric that enables scaling up to 32 cores from X-Gene 2’s mere 8 cores.
What’s Changed with X-Gene 3?
At a core level little has changed from APM’s previous custom ARMv8-compatible X-Gene core. The core’s branch prediction and TLBs capabilities were improved for a claimed IPC gain of approximately 10 percent. The move from TSMCs 28nm process to its 16nm FinFET+ node has enabled major increases in core clock speeds up to 3 Ghz over the 2.4 Ghz that X-Gene 2 offered. Interestingly APM also expects TDPs to be similar to Intel’s Xeon offerings at somewhere between 110 and 125 Watts. X-Gene 3 is also turbo capable when some cores are idle enabling clock speeds of up to 3.3 Ghz in certain scenarios.
The big bang with X-Gene 3 is the uncore which breaks down into improvements in the memory subsystem which is substantially different from X-Gene 2, the enlargement of the L3 cache, the addition of 42 PCI-E 3 lanes, and improved ECC support.
As I mentioned earlier X-Gene 3 supports 8 channel memory at DDR4-2667 with capacities of up to a terabyte and theoretical maximum memory bandwidth of 170 GB/s. This massive investment in the memory subsystem will probably be X-Gene 3’s biggest advantage over competing solutions from Intel, Cavium, and Qualcomm. To improve X-Gene 3’s ability to compete directly with Intel’s mainstream Xeons the company has moved away from integrating Ethernet NICs and other accelerators. Instead it’s offering a pile of PCI-E 3 lanes that OEMs and customers can hook into with whatever they’d like. Finally X-Gene 3’s improved ECC support is a pretty straightforward feature that customers no doubt demanded.
AppliedMicro is also giving out its first hints about the follow-up chip the X-Gene 3XL which will offer 64 cores and a SPECint_rate2006 score of about 1000. Neither the X-Gene 3 or X-Gene 3XL chips have taped out, but APM says that it’s finalized the microarchitecture and they are apparently nearing that milestone. APM expects to sample the X-Gene 3 in H2 2016 and ship it in H2 2017 arriving just in time to fight Intel’s Skylake-based server chips.
Make or Break
APM’s first two X-Gene products on the 40nm and 28nm process nodes were more proof of concept efforts than anything else. But with the X-Gene 3 APM appears to be going for broke with massive core counts, large caches, lots of memory channels, and PCI-E lanes. This announcement comes as Intel appears to be at its weakest point in years with significant layoffs beginning this quarter. If the ARM-based server ecosystem is going to take off it will be products like APM’s X-Gene 3 that take it there. Chip design is no small endeavor and the entrance of ARM in the server market has come in fits and starts with many casualties along the way. Even with APM’s X-Gene 3 and X-Gene 3XL on the horizon it looks like meaningful competition in the server market is still about 2 years away.S|A
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