Originally Posted by Seronx
What I was talking about was defects as a percentage of wafer area. When I first read about 450mm wafers, there was a lot of talk about increased defects due to the problems of dealing with a larger surface that has to be perfectly flat and with layers that are only a few atoms thick. IIRC, there was some speculation that it would be almost impossible to get 450mm wafers to work with any decent yields. Back then, I think Intel was the only one talking about doing it.
For instance, if a 300mm wafer yielded 70% usable dies, might a 450mm wafer be expected to yield only 55% to 65% usable dies of the exact same chip using the exact same processing steps?
I'm a software guy so I might not be using the proper lingo but I hope that what I'm asking is now understandable.