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| CPUs Talk about processors and related technology |
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#1
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Years ago, in a far, far away galaxy called Aceshardware, David Berkgvist (spl?) wrote a little program called CPUCache which attempted to show relative performance for different MPU cores and their caches - the basic characteristics of each could be tooled with in a text file.
Does anyone know of something similar and freely available? I'm really interested to know things like: Effective latency - what impact to bottlenecks have and where do they occur if I monkey with any part of the system. Active ports vs pseudo-porting (true parallel cache cell access vs increased way-count). Cache line length - what affect does the line length have when we place different demands on the cache. If there isn't anything I can get my hands on I'm going to attempt to write my own. At first I'll just try to focus on the basics - instruction throughput for the core given a percentage of branches, loads and stores, a rough access pattern for instructions and data, fixed IPC, pipeline depth, clock speeds for core and uncore, and number of cores. At this stage I'm going to assume the following for two "sample codes": 1) AI/DB/Server code - Instruction: 1/6 branches, 75% predicted/locality, 2/6 loads, 1/6 stores, 1 MB footprint. Data: 300 MB footprint, 70% 128 byte records, 30% 32 byte records, 70% random location for memory access. 2) Desktop code - Instruction: 1/8 branches, 92% predicted/locality, 2/8 loads, 1/8 stores, 2 MB footprint. Data: 50 MB footprint, 20% 128 byte records, 80% 32 byte records, 15% random location for memory access. If anyone wants to chip in with suggestions or recommendations/corrections for my percentages above please drop a comment. Likewise if anyone thinks this would be useful drop me a line or comment, which should encourage me to work faster.
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Long live aceshardware!
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#2
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Hmmm part of the problem with some of those goals is that getting a *really* accurate level of performance is hard. Really hard. Especially given trade-offs you might not know about but are just as consequential; so I guess my question is, what level of accuracy are you looking for?
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Speaking for myself. |
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#3
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Quote:
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Long live aceshardware!
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#4
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#5
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Found it and forgotten it. Thanks for reminding me. (My mum died in the intervening couple of weeks. I'll use that as my excuse anyway - thanks Mum!)
Have you ever used it yourself?
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Long live aceshardware!
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#6
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I used to use it quite a lot, but since it only simulates a single core, and I didn't have the time to extend it to multicore myself, I haven't used it recently.
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#7
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Sounds pretty interesting. I wrote a very very simple version of this a couple years ago for a uni paper (was just looking at performance of cache levels etc.) and would be pretty interested in seeing something that fully tested. Would be interested to help you out with some testing or something if you do go forward with writing your own thing.
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#8
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Some simulators I know are:
PTLSim Zesto-x86 PTLSim has been used to simulate AMD's ASF: http://www.amd64.org/research/multi-...e-systems.html |
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#9
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I remember seeing great CPU cache analysis at Digit-Life.
Digit-Life is no more, but I think the tool they used was related to Rightmark. http://www.rightmark.org/ Memory analyzer there seems to be something you might be looking for. [Edit] There's source code available for the project. While it doesn't exactly generate nice 3D-charts Digit-Life had, it certainly seems to generate pieces of similar information. If this is not what you are looking for, then it might provide good reference or base to build on. It supports threads and aggregate cache/memory performance. Last edited by Rottis; 02-15-2010 at 08:46 AM. Reason: Add information after going through the source |
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| cache, cpu, simulation |
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