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  #1  
Old 08-07-2016, 01:28 AM
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Old 08-07-2016, 04:40 AM
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I think they forgot the "up to 4 Zen cores" when they said "4 zen cores"

At 4W min power. Uh. Well, if AMD can make it happen
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Old 08-07-2016, 04:51 PM
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I think they forgot the "up to 4 Zen cores" when they said "4 zen cores"
4 is the number of cores in one core complex. I'm not sure, if they'll sell partly working core complexes in a chip. Also the latest ES leak at Anandtech's forum had a base granularity of 4.

A core complex might be tightly integrated, similar to CUs in the GPU, where there are also no half enabled CUs. Of course, a CU contains much less logic.
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Old 08-07-2016, 05:03 PM
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I would imagine if AMD wants to aim for very low power, they're going to need to sacrifice either tons of clocks, or some cores.

I imagine they can disable individual cores in the complex?


Although, part of this problem was I misread "up to 16 compute cores" and read that as CUs. So it is up to 4C/12CU.

I suspect at 4W you're looking at 2C/4-8CU (depends if disabling or lowering clocks reduces power more)
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Old 08-08-2016, 01:24 AM
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Originally Posted by Dresdenboy View Post
A core complex might be tightly integrated, similar to CUs in the GPU, where there are also no half enabled CUs. Of course, a CU contains much less logic.
Pitcairn had some of its CUs incomplete.

http://www.anandtech.com/show/5625/a...uthern-islands
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Old 08-08-2016, 02:47 AM
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Pitcairn had some of its CUs incomplete.

http://www.anandtech.com/show/5625/a...uthern-islands
A group of CUs can be any amount. I believe even a lone CU can count.

P11 could be 5+5+5+1 if AMD wanted it to be. Although that would be stupid.
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Old 08-08-2016, 06:38 AM
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Originally Posted by Dresdenboy View Post
4 is the number of cores in one core complex. I'm not sure, if they'll sell partly working core complexes in a chip. Also the latest ES leak at Anandtech's forum had a base granularity of 4.

A core complex might be tightly integrated, similar to CUs in the GPU, where there are also no half enabled CUs. Of course, a CU contains much less logic.
These days we have AVFS and power gating at the granularity of individual core anyway. I don't see why they would go backwards and throw away that flexibility. So selling parts with fused-off cores would hardly not happen.

Last edited by pTmd; 08-08-2016 at 06:41 AM.
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Old 08-09-2016, 07:13 AM
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A core complex might be tightly integrated, similar to CUs in the GPU, where there are also no half enabled CUs. Of course, a CU contains much less logic.
Jaguar:
http://static.betazeta.com/www.chw.n.../Jaguar-CU.jpg
I don't see any reason why they should have less flexibility with the new cores.
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Old 08-09-2016, 11:33 AM
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Jaguar:
http://static.betazeta.com/www.chw.n.../Jaguar-CU.jpg
I don't see any reason why they should have less flexibility with the new cores.
OK, they might technically do it. But there are now 2 complexes in SR, disabling cores in just one of them might cause some imbalances. And disabling cores in both CCX' might create an unusal topology.
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Old 08-10-2016, 04:10 AM
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OK, they might technically do it. But there are now 2 complexes in SR, disabling cores in just one of them might cause some imbalances. And disabling cores in both CCX' might create an unusal topology.
You can always fuse off things symmetrically among complexes, if the only thing being shared by the cores is the L3 cache (incl. the coherent bus interface if you assume they are going for an inclusive L3).

For things within the complex, it depends on the design. If you assume the L3 cache is banked like Jaguar's L2 with a full crossbar, it should be perfectly fine to fuse them off.

Last edited by pTmd; 08-10-2016 at 04:13 AM.
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