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Process technology Here is the discussion for fabs and process tech related to fabs. Please note if you are talking floorplans that belongs in CPUs not process tech.


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  #11  
Old 02-06-2016, 01:16 AM
fullermd fullermd is offline
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Quote:
Originally Posted by Moral Hazard View Post
I'm still not understanding why the BEOL of 14/16nm got nerfed in the first place. As a non-expert in this field there are a few possibilities I can point to and hopefully someone with more knowledge can tell which if any are correct:
As a non-expert in the field, it's my understanding that

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2) Shrinking the BEOL actually does increase the costs so much that it's worth sacrificing the extra production to keep costs down
the next shrink of the BEOL requires pushing multiple patterning much deeper into the metal layers, which means a lot more masks and exposures, which makes every part of the process much more expensive for everyone.
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  #12  
Old 01-16-2017, 10:37 AM
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Interesting read: http://seekingalpha.com/article/4036...anometer-chips
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  #13  
Old 04-19-2017, 09:36 AM
Fottemberg Fottemberg is offline
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According to my sources, Mobile Cannonlake CPUs ( @10nm) are too power ungry. Maybe Intel have to lower the frequencies to show good TDPs.
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  #14  
Old 04-19-2017, 02:11 PM
pmoses pmoses is offline
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Quote:
Originally Posted by Fottemberg View Post
According to my sources, Mobile Cannonlake CPUs ( @10nm) are too power ungry. Maybe Intel have to lower the frequencies to show good TDPs.
For that we have SDP
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  #15  
Old 04-19-2017, 05:55 PM
Moral Hazard Moral Hazard is offline
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Quote:
Originally Posted by Fottemberg View Post
According to my sources, Mobile Cannonlake CPUs ( @10nm) are too power ungry. Maybe Intel have to lower the frequencies to show good TDPs.
I thought the reason Intel was only using 10nm (at least initially) on mobile chips was because the only real benefit of the process (at least big enough to justify the cost) was greater power efficiency.

oops
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  #16  
Old 04-19-2017, 09:30 PM
testbug00 testbug00 is offline
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Quote:
Originally Posted by Fottemberg View Post
According to my sources, Mobile Cannonlake CPUs ( @10nm) are too power ungry. Maybe Intel have to lower the frequencies to show good TDPs.
They may be to power hungry, but not to cause TPD issue.

shhh, sekrit reasons.
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  #17  
Old 04-20-2017, 06:32 PM
x800xtguy x800xtguy is offline
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I think that Intel will fix all their 10nm problems, biggest problem how be research how to make 7nm done then.

BTW 10nm LPP is ready: http://wccftech.com/samsung-10nm-fin...cess-complete/
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  #18  
Old 04-20-2017, 10:37 PM
testbug00 testbug00 is offline
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Quote:
Originally Posted by x800xtguy View Post
I think that Intel will fix all their 10nm problems, biggest problem how be research how to make 7nm done then.

BTW 10nm LPP is ready: http://wccftech.com/samsung-10nm-fin...cess-complete/
Maybe. Just like how their 14nm problems were "fixed" probably.
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  #19  
Old 04-21-2017, 11:32 AM
x800xtguy x800xtguy is offline
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Quote:
Originally Posted by testbug00 View Post
Maybe. Just like how their 14nm problems were "fixed" probably.
That's why i put ready in the message.
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  #20  
Old 04-21-2017, 12:21 PM
testbug00 testbug00 is offline
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Quote:
Originally Posted by x800xtguy View Post
That's why i put ready in the message.
I was referring to Intel, not Samsung. Didn't make that clear, sorry.
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