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  #61  
Old 07-09-2017, 03:53 PM
8088 8088 is offline
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Latest info about Glofo's 7nm LP:

https://www.semiwiki.com/forum/conte...ss-detail.html
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  #62  
Old 07-15-2017, 12:31 PM
Bluefoot Bluefoot is offline
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Quote:
Originally Posted by 8088 View Post
Gonna be a blood bath for Intel and NVIDIA if 7LP hits its targets and Zen2 and NAVI launch H2 '18.
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  #63  
Old 07-21-2017, 02:51 PM
Moral Hazard Moral Hazard is offline
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Quote:
Originally Posted by NTMBK View Post
"7"nm, with only 2x transistor density over 14nm If they had any shame, they would call it 10nm.
I was going through to see the density of the current 14nm and was kind of shocked to read that the 8-core Ryzen has 4.8 billion transistors in a 192mm2 chip.

By way of comparison, Intel's 10-core, 14nm Broadwell-E chip has 3.2 billion transistors in 246mm2.

For Ryzen that's a flat 25 million transistors/mm2. For Broadwell, that's slightly over 13 million transistors/mm2.

That said, that Anandtech number for the number of transistors in the 8-core Ryzen chip certainly smells funny. Not only would the chip be almost twice as dense as its Intel competitor, it would also be about twice as many transistors/core (despite having comparable performance), and about 4 times the number of transistors/core as Bulldozer (despite claims by AMD that it would be the size of a Bulldozer "compute unit", which is 2 cores). My guess is that somebody copied some number wrong and that the actual number is more like 2.4 billion transistors.

Still, if GlobalFoundries' "14nm" is actually twice as dense as Intel's, than a "7nm" that's twice as dense again would be 4 times the density of Intel's "14nm" (the one that Charlie claims deserves the label for some reason), and thus worthy of the name as well.
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  #64  
Old 07-22-2017, 04:33 AM
french toast french toast is offline
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Quote:
Originally Posted by Bluefoot View Post
Gonna be a blood bath for Intel and NVIDIA if 7LP hits its targets and Zen2 and NAVI launch H2 '18.
What is the GPU roadmap for 2018? Is navi a set of chips or just one chip?
For a true turnaround AMD would need a top to bottom GPU launch on 7nm by q3 2018- probably impossible.
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  #65  
Old 07-22-2017, 05:01 AM
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non-Intel foundries have almost always approached their maximum theoretical density than Intel.

Intel's 14nm process is about a "real node jump" in density from their 22nm process.

everyone else 14nm process (excluding IBM?) is about zero improvement from the companies 20/22nm process.
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  #66  
Old 07-22-2017, 11:12 AM
Moral Hazard Moral Hazard is offline
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Quote:
Originally Posted by testbug00 View Post
non-Intel foundries have almost always approached their maximum theoretical density than Intel.

Intel's 14nm process is about a "real node jump" in density from their 22nm process.

everyone else 14nm process (excluding IBM?) is about zero improvement from the companies 20/22nm process.
You seem to be conflating two half-generations. If Intel got a "real node jump" from 22 to 14, then it still lost 1/2 of a node in there somewhere.
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  #67  
Old 07-22-2017, 03:09 PM
testbug00 testbug00 is offline
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Originally Posted by Moral Hazard View Post
You seem to be conflating two half-generations. If Intel got a "real node jump" from 22 to 14, then it still lost 1/2 of a node in there somewhere.
????

You mean how Intel "skipped" 16nm?

14nm is the official name for the node after 22nm from ITRS, I believe.
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  #68  
Old 07-22-2017, 10:04 PM
Moral Hazard Moral Hazard is offline
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Quote:
Originally Posted by testbug00 View Post
????

You mean how Intel "skipped" 16nm?

14nm is the official name for the node after 22nm from ITRS, I believe.
They're the only ones that played that particular name game, not that everybody else hasn't played their own games. TSMC even has a "16nm" node. Yet for all their different naming conventions the actual processes (assuming the Ryzen number is bogus) ended up, if not the same, as least pretty close.
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  #69  
Old Today, 04:04 AM
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AMD’s CTO on 7nm, Chip Stacks

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Papermaster calls for EUV ASAP

Rick Merritt
7/24/2017 00:31 AM EDT

SAN JOSE, Calif. — AMD is among chip designers getting an early taste of 7nm process technologies, said its chief technology officer. He called for accelerated work on wafer-level fan-out packaging and greater use of parallelism in EDA software.

To gear up for 7nm, “we had to literally double our efforts across foundry and design teams…It’s the toughest lift I’ve seen in a number of generations,” perhaps back to the introduction of copper interconnects, said Mark Papermaster, in a wide-ranging interview with EE Times.

The 7nm node requires new “CAD tools and [changes in] the way you architect the device [and] how you connect transistors—the implementation and tools change [as well as] the IT support you need to get through it,” he said.

Both AMD’s Zen 2 and Zen 3 x86 processors will be made in 7nm. “It’s a long node, like 28nm…and when you have a long node it lets the design team focus on micro-architecture and systems solutions” rather than redesign standard blocks for the next process, Papermaster said.

The CPUs and GPUs AMD is shipping today were among its first designs in 14/16nm nodes using double patterning lithography and FinFET transistors.

For that work, “our partnerships with foundries and the EDA industry had to deepen. In 7nm it requires even deeper cooperation [because] we have quad patterning on certain critical levels [where] you need almost perfect communications between the design teams,” he said.

Papermaster expects foundries will begin to use extreme ultraviolet (EUV) lithography starting in 2019 to reduce the need for quad patterning. EUV “could bring a substantial reduction in total masks and thus lower costs and shorten cycle time for new designs,” he said.

“Foundries will introduce [EUV] at different rates but…I urge them all to go as fast as they can,” he said.

To date, AMD has used Globalfoundries, its former fab group, to make its x86 CPUs and TSMC to make its graphics processors. “They have both been aggressive in 7nm and that’s good for the industry. The gap has closed versus where Intel is at and that’s an incredible juncture in the industry that people have predicted and now were seeing it,” Papermaster said.

The latest high-end graphics processors from AMD and rival Nvidia are bringing 2.5-D chip stacks to their broadest set of customers to date. The technique connects processors and memory stacks side-by-side on fast silicon interposers, but it’s still expensive.

Meanwhile, Apple and others are combining mobile applications processors with memory in wafer-level fan-out packages. The so-called 2.1-D technology is not yet suitable for more powerful desktop and server processors, but versions could be ready in two or three years, Papermaster estimated.

“The call to arms here is to reduce the cost of wafer-level fan-out and similar technologies in active development across the industry. There are good demos, but it’s not pervasive, volumes are not high enough yet and we have not achieved the cost points we need,” he said.

Amkor, Shinko Electric, other packaging specialists and foundries have versions of the 2.1-D technology in the works. Intel is using a proprietary approach called EMIB to link server processors and FPGAs. Meanwhile, ASIC makers are gearing up to use the 2.5D stacks that could raise volumes and lower costs for that technique, he said.

The technology is key for “an era of Moore’s law-plus where we’re getting new density advantages at each node and cost advantages as each new node matures, but mask costs are going up and chip frequencies are not going up, so how we put solutions together is critical to sustain the pace of development,” he said.

In software, “my call to action for the EDA community…is to redouble their efforts to take advantage of more CPU cores and parallelism…As the processing required for 7nm escalates…their algorithm optimization needs to take advantage of the very technology they are helping us manufacture,” he said, noting AMD’s new Epyc processors sports 32 dual-threaded cores.

“Mask data post processing is highly parallel, and I’m starting to see good enhancement there. I’d like to see it extend to physical design and verification where we spend a lot of resources,” Papermaster said. Meanwhile, AMD has “embraced emulation as a way to accelerate our verification and marry co-verification of software and hardware,” he added.

It’s one of many ways AMD has been punching above its weight to compete with rivals Intel and Nvidia.

“In our turn around, we couldn’t just throw hundreds of designers at a problem, so we designed in more modularity to reuse circuits across client CPUs, GPUs and semicustom chips…We stayed on and even improved time from first silicon to tape out as complexity went up with FinFETs and…verification complexity,” he said.

“The AMD team has always been known for deep talent. We hit a point where we had to pull together to build great products, and there was no room for in-fighting,” he said.
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