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Old 01-23-2017, 12:49 PM
raghu78 raghu78 is offline
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Default TSMC confirms 7nm EUV in 2019

http://www.tsmc.com/uploadfile/ir/qu...transcript.pdf

Excerpt from TSMC Q4 2016 earnings call

Mehdi Hosseini - Susquehanna Financial Group - Analyst
Okay. Then when we look into 7 nanometer and some of your competitors have a different definition of 7. Can you help us understand how your N7, compete and is positioned against your competitors?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Senior Director, TSMC Corporate Communications Division
So Mehdi is saying that our 7 nanometer definition is different from other companies' 7 nanometer definition, so how do we compete at 7?

Morris Chang - Taiwan Semiconductor Manufacturing Company Ltd - Chairman
Our 7 nanometer definition is different from somebody else's? Well, I'll let Mark answer.

Mark Liu - Taiwan Semiconductor Manufacturing Company Ltd - President and Co-CEO
I wouldn't want to comment on other people's 7 nanometer. Our 7 nanometer is under qualification now and it will be qualified as according to plan from the end of first quarter. And we have already more than 20 customers design-in on this 7 nanometer and this year alone we estimate will be 15, 20 tapeouts already. So this is our momentum build so far on a seven nanometer and no other competitor is getting to this stage of this leading edge technology. So we have -- we are to -- remember I mentioned last time we'll have 5 nanometer two years from now and forget about the name. That will be a full node shrink and that will sit competing well with any technology come out at that time. Okay, let me add some on 7 nanometer. We will maintain our 7 nanometer competitiveness just like we do on 28 and 16. We will have a technology currently planned as 7 nanometer but with the EUV insertion in the second year of 7 nanometer, just one year -- approximately one year after. And that can greatly simplify the process and without increase the cost. And that is if customer can take advantage of minor design it can further reduce their density -- increase their density and reduce their die cost. That is our plan to maintain that competitiveness of the 7 nanometer the year after. So we think 7 nanometer is a well adopted node by all the customers and we plan for the subsequent technology to shore up the demand continuously. And we hope to use this technology -- I mean the second-year technology to prepare for the EUV production experience for the full fledged EUV technology on 5. Then our customers can have a very hopefully smooth getting to from our 7 to our 5 nanometer technology. So that is how we maintain our technology competitiveness.

Mehdi Hosseini - Susquehanna Financial Group - Analyst
May I ask a clarification question?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Senior Director, TSMC Corporate Communications Division
Sure.

Mehdi Hosseini - Susquehanna Financial Group - Analyst
I think if I heard you correctly is you will insert -- if I heard you correctly you said you will insert EUV in this second year of your 7 nanometer, which suggests to me that you may actually be able to commercialize (technical difficulty) conclusion here?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Senior Director, TSMC Corporate Communications Division
Mehdi, I'm afraid that your voice was broken at some point in time. Can you please repeat? We heard you, that you said that we will insert EUV in the second year of 7 nanometer and then you had something but it was cut off. Can you repeat that part?

Mehdi Hosseini - Susquehanna Financial Group - Analyst
Sure. Yes, sorry about that. I just wanted to make sure I understand the EUV commentary correctly. You said that you will insert EUV in the second year of 7 nanometer. That suggests to me that you may actually be able to insert EUV before competitors that have said insertion would happen at 5. Is that the right conclusion as we compare and try to better understand your competitiveness at 7 nanometer?

Mark Liu - Taiwan Semiconductor Manufacturing Company Ltd - President and Co-CEO
Yes, we will commercialize the 7 EUV in the second year of our 7-nanometer production. I wouldn't comment on when will our competitor insert their EUV. That is -- I don't intend to do the comparison here.


TSMC's 7nm EUV products should be out in H2 2019. AMD has a lot of choice and flexibility now that they have amended WSA. I am keen to see AMD CPUs produced at 7nm EUV go up against Intel's 10nm products in late H2 2019 or early 2020. Intel is going to face the most stern competition it has ever faced from TSMC in the process node race. TSMC has also said it intends to ramp 5nm with EUV in 2020.

Last edited by raghu78; 01-23-2017 at 12:57 PM.
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Old 01-24-2017, 06:54 AM
carop carop is offline
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Quote:
Originally Posted by raghu78 View Post
Okay. Then when we look into 7 nanometer and some of your competitors have a different definition of 7. Can you help us understand how your N7, compete and is positioned against your competitors?
So, it took three people to sidestep that question. Moving from 10FF to 7FF, they do not appear to be scaling the metal interconnect. But, why not be honest about avoiding quad pattering (SAQP) on the most critical metal layers?

The new foundry 7nm logic node was supposed to be represented by a gate pitch size about 45nm and a metal pitch size about 32nm. They might as well have called this 7FF process 10FF+.

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Old 01-24-2017, 08:54 AM
JeeBee JeeBee is offline
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I wonder where TSMC 12nm fits there - it appears to be a 16/16 FEOL/BEOL node.
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Old 01-24-2017, 10:04 AM
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12nm is a 16FFC evolution.
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Old 01-24-2017, 10:12 AM
raghu78 raghu78 is offline
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12nm is a 16FFC evolution.
True.

Randy Abrams - Credit Suisse - Analyst
Yes, if TSMC has a strategy or plan to introduce an in-between 12 nanometer to protect share on the FinFET for customers not going to 10 or 7?

C.C. Wei - Taiwan Semiconductor Manufacturing Company Ltd - President and Co-CEO
Okay. In fact, we -- our strategy is continuously to improve every node in the performance, such as 28 nanometer. And we continue to improving the 16 nanometers technology. And we have some very good progress, and you might call it the 12 nanometer because we're improving in the density, logic density, performance and power consumption. Yes, we have that.
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Old 03-20-2017, 10:57 AM
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TSMC’s 7nm Risk Production Will Start In April; 7nm+ Will Use EUV, With 1.2x Logic Density & 10% Performance Boost Over 7nm

http://wccftech.com/tsmc-7nm-proces-sram-details/
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Old 03-21-2017, 03:17 PM
x800xtguy x800xtguy is offline
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It seems that all the three fabs will get their newer processes in time.


And Samsung is already studing GAAfet(another fet technology to superate Finfet benefits) for 10nm already.


Both of them are beeting their own expectations, let's see if GF can bring the 7EUV on 2H2018 as promised.

Last edited by x800xtguy; 03-21-2017 at 03:19 PM.
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Old 03-21-2017, 11:44 PM
Moral Hazard Moral Hazard is offline
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If Samsung is seeing little performance gain, but good power savings at 10nm, with bigger performance gains at 7nm, I'm wondering if maybe AMD will use them (or possibly TSMC) at 10nm for their mobile chips while waiting till GF releases their 7nm process to update their desktop and server chips.

I know their wafer supply agreement with GlobalFoundries includes a penalty for using another supplier, but presumably the penalty diminishes the more chips are made at GF. Indeed, if they managed to somehow max out GF's production it wouldn't make sense for them to pay any penalty at all after that, though I don't know how close to max GF is running.
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Old 03-22-2017, 09:52 AM
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Quote:
Originally Posted by Moral Hazard View Post
If Samsung is seeing little performance gain, but good power savings at 10nm, with bigger performance gains at 7nm, I'm wondering if maybe AMD will use them (or possibly TSMC) at 10nm for their mobile chips while waiting till GF releases their 7nm process to update their desktop and server chips.
Samsung 10LPE versus 14LPP on SD821 seems to be about 25% power savings including anything Qualcomm got for a fixed VR workload from anandtech performance preview.
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