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  #931  
Old 05-27-2013, 07:49 AM
inf64 inf64 is offline
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Finally Hans posted. We appreciate your input very much Hans
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  #932  
Old 05-27-2013, 07:49 AM
TESKATLIPOKA TESKATLIPOKA is offline
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ROM is in the centre of L1I cache If I am not mistaken.
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  #933  
Old 05-27-2013, 10:41 AM
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Quote:
Originally Posted by TESKATLIPOKA View Post
ROM is in the centre of L1I cache If I am not mistaken.
Well, normally I would expect some Cache-TAGs in the middle between two cache banks. So I am not convinced here. Or maybe the middle part is just the area for the loop-cache? In Kabini the loop-cache uses parts of the instruction cache. Another candidate could be predecode-bits. ROMs so central wont make sense imo. But I am not sure either.

Just re-read paper about the integer-cluster in the BD-ISSCC paper:
Quote:
The execution unit supports single-cycle operand bypass from an instruction to a dependent instruction. Two ALU ops and two AGU ops can be executed in a cycle. AGU ops include increment/decrement (INC), address generate, and x86-64 LEA instructions. The ALUs and the INC units participate in single-cycle operand bypass. Four result buses, one from each of the units, feed four writes ports into the PRF. Each execution unit can receive data from any of the four write ports or from a PRF read. Each execution unit has two sources, requiring eight read ports in the PRF. To remove wire delay (and congestion) from the critical bypass path, the PRF is duplicated. The register file is divided into halves; the critical half, further from the output driver, has fewer pull-downs on the local bitline, reducing slew rates on critical words with minimal area impact (Fig.4.6.6). Duplicating the INC removes the vertical wire delay from the worst-case bypass path, which is from any INC to the far ALU.
Guessing from that, I would say, that we dont have 4way operation, but just 2x2, where the first AGU works together with the first ALU, and the 2nd units accordingly, because the vertical wire delay would too high.

However, the quote is from the Bulldozer presentation, who knows if AMD's engineers found a solution for the mentioned delay problem for that new chip, be it Steamroller or Excavator.

Last edited by Opteron; 05-27-2013 at 10:44 AM.
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  #934  
Old 05-27-2013, 05:50 PM
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I got a weird idea that this shot might have possibly been leaked from AMD's Hot Chips presentation? It's relatively close, in July I think (or around then).
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  #935  
Old 05-27-2013, 06:57 PM
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Is it possible AMD delayed the chip a few months to get this out to FX platform? It'd make sense to coincide with the giant push for gaming, and FX 8150 and FX 8350 came out in October, yet Steamroller FX is rumored for Q1 2014, missing the early date and being delayed.

It's not like people are going to swarm to Haswell for gaming rigs, but a 30% IPC increase and 5 modules would move a lot of chips in the enthusiast market, whatever that's worth.
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  #936  
Old 05-27-2013, 07:25 PM
itsmydamnation itsmydamnation is offline
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Hotchips is late aug, if this is a real core shot you would have to think this is the chip that is being sent to developers soon. You would also think that they would be firing up the press now for production runs.
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  #937  
Old 05-27-2013, 08:38 PM
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Quote:
Originally Posted by sdlvx View Post
Is it possible AMD delayed the chip a few months to get this out to FX platform? It'd make sense to coincide with the giant push for gaming, and FX 8150 and FX 8350 came out in October, yet Steamroller FX is rumored for Q1 2014, missing the early date and being delayed.

It's not like people are going to swarm to Haswell for gaming rigs, but a 30% IPC increase and 5 modules would move a lot of chips in the enthusiast market, whatever that's worth.
Doubtful. AM3+ is most likely dead.
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  #938  
Old 05-27-2013, 09:29 PM
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Originally Posted by NTMBK View Post
Doubtful. AM3+ is most likely dead.
It won't make much sense to release a new socket with DDR4 so close, forcing AMD to change socket again.

Unless DDR4 is be released to consumers this year, or AMD somehow make a socket already compatible with DDR4 (possible, but slightly risky), AMD will wait for DDR4 before releasing a new socket.
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  #939  
Old 05-27-2013, 10:34 PM
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Originally Posted by sirroman View Post
It won't make much sense to release a new socket with DDR4 so close, forcing AMD to change socket again.

Unless DDR4 is be released to consumers this year, or AMD somehow make a socket already compatible with DDR4 (possible, but slightly risky), AMD will wait for DDR4 before releasing a new socket.
a) There are pretty convincing rumours of GDDR5 with Kaveri.

b) Who said anything about a new socket? FM2 works just fine- its a far superior platform to AM3+. The only think they need to change is the vast amount of board that the socket and heatsink mounting area takes up- if they went LGA, they would be able to fit onto mini-ITX boards much more comfortably.
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  #940  
Old 05-28-2013, 12:41 AM
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I thought as far as AMD sockets go, that people were expecting Steamroller FX AM3+, a sort of "FM2+" for Steamroller APUs, and then for the sockets to become one after that generation?

If AMD can deliver 20% more performance in am AM3+ package, there's going to be a ton of AMD guys who are tired of being behind Intel that just have to drop a new chip in their motherboards, it'd sell a decent amount of chips, specially considering the FX 6300 gaming rigs and such.
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