SuVolta to take on Intel’s FinFET transistors

Claims 50 percent power reduction at a 22nm node.

On October 25 SuVolta’s Chief Technology Officer is set to present at ARM’s TechCon in Santa Clara, CA. Scott Thompson will compare FinFET, SOI and bulk CMOS.

This is especially interesting as SuVolta has just recently announced its Deeply Depleted Channel (DDC) transistor technology and PowerShrink low-power CMOS platform, which is supposed to cut power consumption by up to 50 percent.

The power saving is similar to what Intel expects to achieve with its FinFET’s, but there is the major difference that SuVolta’s solution is a planar solution and therefore does not require a special fab for manufacturing. Also not using SOI means that the company can use standard wafers instead of the more expensive FDSOI wafers.

SuVolta is currently working with Fujitsu and others to realize its new technology.  As stated, on October 25 we will hopefully be a lot wiser. And SemiAccuate will of course be at the conference.S|A

Updated: same day as publication to deal with typo “not” now included for your pleasure.  Thank you to J. for emailing.

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