ST-Ericsson will later this week present a paper detailing the first three-layer chip involving logic. Previously only memory dies have been stacked. The 2.5D chip will consist of two processor dies as well as a single wide I/O DRAM die, according to a press release from the company.
The design is the result of a close collaboration among CEA-Leti, ST-Ericsson and Cadence Design Systems.
The design integrates three stacked dies, integrating a Wide I/O DRAM memory stacked on top of two identical SOC logic die that incorporate multiple processor cores on each die. TSVs (through-silicon vias) connect these three die together and in order to minimize the impact of the TSVs on signal integrity, the 2.5D stack employs an asynchronous Network on a Chip (NoC) for both die-to-die and intra-die communications, according to information from ST-Ericcson.
For its part of the joint project, ST-Ericsson developed WIOMING, the first application processor SOC integrated with a Wide I/O memory interface.
The ST-Ericsson Wioming SOC provides 12.8GBytes/s of memory bandwidth – a 50 percent increase over the latest available dual channel LPDDR2 solutions at 533MHz at 20 percent less power.S|A
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