Every once in a while, a company will do something really unexpected, like IBM’s laying down the law in packaging last week. Yes, they showed off a chip, two actually, that does things no one else is even talking about doing.
If you look at the chips below, you will see, well, a really advanced packaging set-up. How advanced? Well, this is four CPU dies on an interposer, and not a small interposer at that. Each black spot is a 32nm multi-core die, and a very hot one too? How hot? Well, the chips below are the first Power 7+ parts spotted in the wild, so think really stinking hot.
Power 7+ package minus lid
To be specific, the two on the left are four P7+ dies on an interposer, and that is mounted to a ceramic package far left, organic to the right of that. On the right, there is an unnamed stacked die chip with and without lid. This means IBM can stack die directly, do a PoP on both ceramic and organic, and most importantly do it on a higher power part than anyone else will ever need. We won’t mention reliability, if there was any question about that, IBM wouldn’t put it on Power chips, those customers don’t cherish their downtime. It’s one of the few platforms deemed too reliable for Windows.
OK, so IBM is laying out the law on advanced packaging, and no one else has shown this type of tech, not to mention anything on this scale. Could it get any better? Sure it can. What if I told you that the interposer wasn’t a passive part, but an active one with lots of embedded RAM. Need a few, oh, lets say tens of MB cache with a silly wide interface? See above. Also see your local IBM rep because no one else can do this.S|A
Latest posts by Charlie Demerjian (see all)
- Intel shows off 10nm 112Gbps SerDes - Mar 12, 2019
- Intel releases Compute Express Link spec - Mar 11, 2019
- Qualcomm rolls out a second gen 5G modem called X55 - Feb 19, 2019
- What is Intel’s Foveros tech and what isn’t it? - Feb 11, 2019
- Why SemiAccurate called 10nm wrong - Jan 25, 2019