Intel is going code name crazy during IDF Beijing and is teasing three Atom code names. If you are expecting any actual information you will be sorely disappointed, this is an IDF presentation after all.
The first code name isn’t all that new, SemiAccurate brought you the name Avoton almost 6 months ago, nearly three times that long if you don’t count spelling mistakes. Centerton is the brand for Xeonized Atoms like Avoton, Intel announced it long ago too, but the code names Briarwood and Rangley are new. This being an IDF, those three names are the majority of the news, but there is a little more background can tell you about.
Briarwood or Atom 12×9 is a storage oriented SoC based on the current 32nm cores. This line takes a current Atom, slaps 40 PCIe2 lanes on it, then adds some RAID hardware and crypto logic too. While both sound impressive, an XOR engine is not a big deal, and the crypto blocks are likely pilfered from mainstream CPUs, a good thing there. Briarwood isn’t a new project as much as a benefit of modular designs and component reuse to address new markets.
If this news makes you think, “Hey wait, Intel has promoted Atoms as perfect for this market for a while now and they failed in a painful but public way”, you understand the reason for the above chip’s chances as well. The RAID and crypto logic will help a bit here, and given the almost negligible die area for RAID and crypto you have to wonder why they aren’t just standard on all Atoms. The down side of this is that crypto is not used often if at all in the low end NAS markets Briarwood is aimed at, and the RAID logic wasn’t the problem either. It doesn’t hurt either though.
That brings us to the addition of the PCIe lanes, 40 PCIe2 lanes are a lot, that should fix things, right? Actually not, while it is not quite useless, you have to wonder why Intel bothered. The problem with Atoms in this market is that they are simply underpowered for raw CPU performance. XOR and RAID hardware helps a bit, but the thing is still a dog. Adding more PCIe lanes does not address this, a crap chip with 40 PCIe2 lanes is a crap chip with overkill I/O that it can never hope to use.
To make matters worse, the old Atoms fell over with a 4-bay NAS when using the same core as Briarwood. Lets assume the magic pixie dust sprinkled on this part means Briarwood doesn’t fall flat until it hits eight drives. We won’t write a treatise on why SSDs in a NAS is dumb, but you might have noticed that the 1Gb pipe off the back is a tad slower than a single 6Gb SATA port, a 10Gb pipe is slower than two ports, and most homes or small businesses don’t have GbE running much less end to end 10GbE. A fast magnetic drive can push about 125MBps, call it 1Gbps, so eight will use less than 10Gb of bandwidth. That is two PCIe2 lanes, if you double that to account for external I/O, double it again for everything else, how far from 40 lanes are you? Eight would be massive overkill so you have to wonder why the die space was wasted for this many lanes. Don’t look for greatness with Briarwood, avoiding abject failure will be a high enough bar.
Rangley on the other hand is really new, it uses the upcoming 22nm Silvermont core just like Avoton. This part is aimed at the comms market instead of microservers though, think low end routers, Wi-Fi boxes, and the like that ARM SoCs dominate now. Intel added a crypto and I/O acceleration block in an attempt to counter ARM’s dominance in this space but still cannot address the margin problem. See 12×9 for outlook, it will do just peachy until the 100%+ MDF money goes away, then they are competing against <$10 ARM SoCs with chips built on a process that costs what again? 100% bespoke hardware on a cheap process vs some bespoke hardware on an expensive process is not a fair fight. Goodnight.
And that sums up why we think these parts, technically nifty though they may be, have absolutely no chance in hell of winning. Intel flat-out charges too much, they have to. If they don’t they are using the die space for something with margins that pale against even a low-end desktop CPU. Worse yet the die size of the 32nm products is on par with a dual core A9 with a huge GPU, roughly the same 80-90mm^2 range of a dual core Core iSomethingmeaningless. Once the MDF subsidy money funnel stops or even slows, game over for Atom. There doesn’t seem to be a chance in hell for success long-term, the economics simply don’t work no matter what the official smoke and mirror based claims are.S|A
Latest posts by Charlie Demerjian (see all)
- Intel shows off 10nm 112Gbps SerDes - Mar 12, 2019
- Intel releases Compute Express Link spec - Mar 11, 2019
- Qualcomm rolls out a second gen 5G modem called X55 - Feb 19, 2019
- What is Intel’s Foveros tech and what isn’t it? - Feb 11, 2019
- Why SemiAccurate called 10nm wrong - Jan 25, 2019