SemiAccurate has already talked about the Silvermont core and architecture, now it is time to take a look at the process it is built on. We have already looked at some of the process, but Intel recently gave out a little more detail.
Lets take a look at the new bits that make up the Intel P1271 22nm SoC process, the first of which was some details about multi-gate transistor spacing. When we first talked about Intel’s 22nm process, we mentioned that some characteristics were tuned by adding a second, third, or more transistor in parallel with the first. This allowed step changes to parameters but in a quantized way. The new detail is that the fins can be spaced quite closely at 22nm, 60nm apart to be exact, for multi-gate transistors.
Related to this are some numbers Intel put on a cross-section of their fins about sizes. The fin itself has an 8nm width in the middle of the sloped sides and that does not include the width of the gate dielectric or the oxide layer. If you add the entire width of the device, it is somewhere between 2-3x that 8nm. It was also listed as 34nm high, again without the gate, which adds somewhere around 5-8nm to that figure. For the semiconductor stat junkies this stuff is important, if you are a normal human it might win you a bar trivia contest sometime if you are really lucky in a strange bar.
One chart to rule them all, one process to bind them
This next slide has a lot of important bits to it, and sums up most of the process work Intel is doing nicely. The bottom is lowering leakage, IE non-dynamic power use. The FinFET process takes care of most of that, greatly lowering leakage. Dynamic power is another issue entirely, but it is also somewhat related. Everything comes down to transistor types and where to use what type.
Four transistor types per process
All transistors for a given process lie on a leakage vs performance curve like the one above. Intel takes that curve and makes four distinct transistor types that can be tuned in a performance window. CPUs generally use the top two types, SoCs use all four. By carefully picking what goes where on a circuit level, Intel can use high performance only when needed and drop leakage for the rest.
Related to this is operating at different voltages. FinFETs have some problems with scaling Vt, and Tri-Gate transistors are no exception. To deal with this, Intel does two things, double the oxide layer and lengthen the gate. We talked about both earlier, and this is what Intel means by the top of the slide, raising the voltage ceiling.
On the left is higher density logic and interconnect, the three 60nm fins spacing for multiple parallel fins is only part of it. As you can see above, there are multiple schemes for metal layers at Intel, 9 or 11 being only part of it. You can also choose between high and low density layers at several of the layers individually to suit the specific needs of your project. The difference in density between a loose pitch and a normal one is about 2-3% but tight pitch can be twice the density of normal if need be.
Available blocks to make an SoC out of
The last part is the non-transistor components that you need to make an SoC. If it isn’t obvious, an SoC process needs to have these components available and P1271 does just that. Most importantly, the 22nm process is said to significantly improve analog performance over the 32, 45, and 65nm processes that preceded it. As you can see from the list above, the components available to the SoC designer is fairly extensive. Speeds, voltages, passives, and memory are there and plentiful enough to keep a fleet of interns or a small shell script busy testing options for an entire summer.
Not much of what Intel said is exactly new, but some of the numbers fill in a few useful blanks. Overall the company gave a lot of the reasons for why P1271 is not just different but also better suited to Atom than the P1270 CPU process that preceded it. In this case, the devil is indeed in the details.S|A