Cypress today is releasing the new GX3 USB3 Ethernet chip and talking about other USB-C silicon. Together this trio has a lot to offer designers in the impending world of USB-C connections.
The basic idea of a USB to Ethernet bridge is not exactly a new one, you can buy USB to Ethernet dongles at almost any electronics store for well under $20. If Cypress is adding a new one with the GX3, what do they bring to the table? In short throughput, energy efficiency, and driver support. The last one is not exactly new to the GX3 but Cypress claims to have Windows XP-8.1, CE 5-7, Mobile 5-6, OSX 10.6-10.10, Chrome 42 and below, Linux 2.6.25-4.0.4, and Android 3.x-5.1.1 support. By the time you read this, several new OSes will be out, Windows 10 included, and they will probably be supported too.
What a USB Ethernet dongle looks like
That list leaves us with two other feature sets, and lets start with throughput. A typical PCIe based GigE adapter will have throughputs of ~950Mbps or so, Cypress claims their GX3 can push about 910Mbps over USB, notably better than the competition. One way they do this is to put a controller on the GX3 that is smart enough to combine Ethernet packets together and do the same for USB.
As you know there are various sizes for Ethernet packets and each has a header along with a bit of back and forth chatter with every packet sent. If you combine these into a “supersize” Ethernet packet which encapsulates several smaller packets, the net back and forth, and thus overhead and latency, can be reduced. Each one of these can be encapsulated into a USB data packet and those can be combined into a single USB Microframe. This allows many packets to be sent in one transaction and then decompressed once across the wire saving a lot of bandwidth sapping chatter.
Last up is the energy savings modes and they come from both the USB and Ethernet interfaces. There are five modes ranging from 7.4mW in USB suspend and no Ethernet plugged in to 623mW in the GX3’s highest activity and throughput state. Between them there is a range depending on USB idle states and Ethernet activity levels. This is possible via Energy Efficient Ethernet aka 802.11az and USB3 low power states.
This will be inside your PD cable
From there we have the CCG1 USB-C port controller with USB-PD functionality. This one is a bit out of the ordinary because it has a programmable microcontroller on board, in this case an ARM Cortex-M0, and some flash. It will support two USB-C ports and needs no external controller or programming for said chip, that is all included. Better yet one of the main points of the CCG1 is to simplify the device design, it needs only 9 resistors and 1 capacitor to make a device, quite a bit less than previous generations of controllers.
While programmability and low BoM costs are good, it is not worth the savings if security is put at risk due to malicious code uploads. We asked Cypress about this and they had a good response to that problem, or more to the point 3+ responses. The CCG1 can have fuses blown to stop code uploads, can use checksums to verify code, and also programmed to not accept further updates after the one just pushed out. While these mechanisms are much better than we expected to find, the last one, the + in the 3+ is better still. In future iterations of the line, Cypress is going to implement a real authentication mechanism for code updates, that will go a long way to slowing down the black hats.
The last new chip is called the CCG2 and it too has the same M0 and programmability features as the CCG1 but is otherwise much simpler. Technically the CCG2 is a USB-C Cable Controller, something that you probably have never heard of. USB-C’s new features, mainly USB-PD, require a smart cable with an authentication mechanism. The reason for this is that if you are going to send 100W of power over a wire, you want to make sure that not only the other side can take it but the cable can too.
The solution to this potential hot spot of engineering was to put an IC in the cable to both check that it is certified, and to signal the sender how much current it is capable of safely passing. It is a tiny chip that can fit in a USB-C cable end and doesn’t do much if anything once the safe voltage levels are established.
Cypress has two cable reference designs with CCG2s in them, a one chip and a two chip design. Since these devices simply negotiate power and pass security validation to the power sending controller, why would you need two of them in a single USB cable? The answer is pretty simple, since the chip needs to be powered to work, it has to be connected to the side that supplies the voltage to turn on.
If you don’t want your USB-PD cable to be directional, you need to put a chip on either end or run an extra wire from one end to the CCG2 on the other end to power it. In some cases a second CCG2 will cost less than an extra run of copper wire needed to deliver that initial voltage to the chip. Doesn’t that put the device cost into perspective, a few meters of copper wire costing more than an IC. Then again the whole device is ~3.3mm2, that is 50% smaller than it’s predecessor, and likely built on a rather old process.
Speaking of processes, the new GX3 is built on an unspecified 90nm process in a non-Cypress fab. The CCG1 Type-C controller on the other hand is built on an older 130nm process at a Cypress fab, an M0 and USB logic doesn’t need much more. If you think about it, 3.3mm2 devices would be pretty badly pin bound if you shrunk them any more so if a 130nm process is fast enough, smaller is only detrimental. The world of device controllers is very different from high-end CPUs and GPUs, very different.S|A
Latest posts by Charlie Demerjian (see all)
- AMD shrinks GPUs to 12nm with the Radeon RX590 - Nov 15, 2018
- Coolit water cools Cascade-AP CPUs - Nov 14, 2018
- Intel tries to pretend they have 5G silicon with the XMM 8160 - Nov 12, 2018
- AMD’s Rome is indeed a monster - Nov 9, 2018
- Intel announces Cascade Lake-AP MCM - Nov 5, 2018