How much of a shrink will TSMC’s 10nm process really provide? SemiAccurate found a datapoint that has all the information needed to figure this one out.
As with all PR based naming schemes, TSMC’s 10nm process should be a better than Moore’s Law shrink if it is delivered in the normal two-year time frame. Why do we say that? If you calculate the shrink, (10 * 10) / (16 * 16) = .39 or ~40% of the previous process aka a 60% shrink! That is an astounding number in this era of shrinking gains, pun intended. Better yet, like Samsung’s 14nm process, TSMC’s 16nm process is effectively the 20nm process with FinFETs and the same BEOL.
What this means is that if Samsung got ~10% from their 20nm -> 16nm ‘shrink, TSMC likely got roughly the same. Lets be charitable and double that to 20%, and if you use that to work the above equation backward, 16nm should really be called 18nm, and again that is using shrinks we feel are overly charitable.
Since a shrink of 20nm to 18nm or 19nm isn’t the stuff of PR dreams much less non-mocking headlines, TSMC, Samsung, and Globalfoundries all picked the numbers it should have been if the shrink was real. That would be 14nm or 16nm. The only company that actually did do a real 20nm -> 14nm shrink is Intel, none of this applies to them, they did the right thing for the right reasons.
So is TSMC’s 10nm process a real 10nm ‘Intel-like’ 10nm process, a better than Moore’s shrink from 16nm, two real 50% area reductions from 20nm, or something else? We found a bit of information unrelated to TSMC that lays this out in no uncertain terms.
Note: The following is for professional and student level subscribers.
Disclosures: Charlie Demerjian and Stone Arch Networking Services, Inc. have no consulting relationships, investment relationships, or hold any investment positions with any of the companies mentioned in this report.
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