ARM is announcing their lead partner for 7nm Artisan IP and it is none other than Xilinx. This one took SemiAccurate by surprise because while FPGA vendors are the traditional lead customers for a new node, partnering with ARM is a new twist.
The headline is pretty simple, the first 7nm chip from TSMC bearing ARM Artisan IP, not POP mind you, just Artisan, is going to be an unnamed Xilinx device. Given that ARM is involved and it is a halo product for both firms, you can also be pretty sure it will be a Zynq device, not a generic FPGA like Virtex. So what is new in this unnamed device with unknown capabilities on a named but not detailed process? Lots, but all is of course in the how, not the what of things.
Lets start out with what ARM is providing for their Artisan offerings on 7nm, currently to Xilinx but soon to many more customers. It starts out with the usual standard cells, memory compilers, and GPIOs but there are differences in the how. Normally IP like this deals with the transistors, lower metal layers, and tries to keep things as compact as possible. This time around ARM is paying a lot more attention to the inter-block and cell to cell connections. Why? Partially because as geometry lowers things get harder, and partially because they need to keep customer costs sane.
This meant a lot more emphasis on BEoL design with more porosity in the lower metal layers specifically M2. This allows for cell to cell routing without using higher and/or more metal layers. Why is this important now? ARM is putting a lot more emphasis on cell based memory designs which allow for more regular designs with less variation for better yields and binning. It also allows memory to be pushed more to the periphery of a design if needed. If you want to reap the benefits of cells, you need to connect them otherwise the added metals will blow out your cost and potentially yields.
Cells or custom, that is the question
Better yet by putting more emphasis on metal layers and routing between standard cells and blocks, ARM gives a lot more flexibility to the end customer. That would be Xilinx in this case, and FPGA are a good use case for lots of connections. Backing this up are a lot of new memory cell types which no designer tends to complain about.
That brings us to PPA or Power Performance Area, essentially the key design parameters for any modern silicon project. At 16nm ARM released a tool for power grid generation called the ARM Artisan Power Grid Architect (PGA). It worked and the learning from that tool went into the second gen PGA which is now available for 7nm TSMC products. Not surprisingly, Xilinx is using it for this 7nm project, what are the odds? This is of course aided by the work on underlying metal layers, there is now less to avoid up high.
Speaking of power and moving it around, the last major block of the project is the GPIOs. If you have read this far, you are probably aware that as geometries shrink and voltages drop, high voltage I/Os become a tricky endeavor. ARM is offering both 1.8v and 3.3v GPIOs as part of the Artisan mix so customers don’t have to do the messy stuff. It may not be all that headline grabbing but getting signals on and off a chip tends to be important to some users.
So that is what is behind the headline, a lot of detail work. This and much more allows Xilinx to be the first out of the gate with ARM Artisan IP on TSMC’s 7nm process. What exactly they will make, when it will be released, and if it comes in more flavors than the usual chocolate, vanilla and strawberry this time is yet to be determined. Hopefully they will release all the higher level data soon.S|A