Intel has not released Skylake-SP die shots and areas for a good reason, margins. Join SemiAccurate for a quick romp through Intel’s ‘top sekrit’ Skylake-SP die shots, areas, and efficiency… or lack thereof.
During their server workshop Intel was keen on trashing AMD’s purported performance with Epyc, something AMD responded to directly at their launch days later. The Intel numbers and presentations were quite accurate, on the measurable numbers, but the rest was over the top. AMD didn’t answer that part but if you look at the performance of Epyc, performance per dollar, and outright socket performance, that answered the pundits quite comprehensively. AMD is either very close on anything but single threaded apps, something 8-core+ devices are not usually purchased for, or outright wins. For a fraction of the price.
AMD gave out die sizes, die shots, transistor counts, and all the rest with their launch. Intel has suddenly decided, after 30+ years of releasing die sizes, dies shots, transistor counts, etc., that this information is now secret. As SemiAccurate said in an earlier article, this is a self-inflicted wound.
So what are the die sizes, and what do the dies look like? Enjoy.
Note: The following is for professional and student level subscribers.
Disclosures: Charlie Demerjian and Stone Arch Networking Services, Inc. have no consulting relationships, investment relationships, or hold any investment positions with any of the companies mentioned in this report.
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