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Thread: AMD aimed to have APUs at 5800 GPU level in 2013

  1. #11
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    Sorry, so you mean Kaveri 'dual graphics' could be about the same as an HD5830 ? So that would be about the same as a GTX580m ? But presumably with the ability to seamlessly powergate the dGPU when not in use ? Thanks. I think I could probably live with that in a mid range notebook...

  2. #12
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    Quote Originally Posted by TESKATLIPOKA View Post
    pTmd
    Rottis with DDR3 performance should look like this depending on actual IGP clocks.
    http://www.notebookcheck.net/AMD-Rad...M.72678.0.html
    Just for kicks I dropped in my 5850 and ran P score, then noticed I have kind of old 1.0.0.0 version.
    Anyhow, 3DMark 11 pro 1.0.0.0 with stock 5850 and stock 8120 gives total score of P3784.
    Kind of far ahead of 7730M scores.
    "One solution that seems to have been reasonably effective in the past is that of public ridicule." - Alex Smith (2014, Nethack 4 about game balancing)
    "VR has been the future of gaming for the last 25 years, and will continue to be for another 25 years..." - NTMBK (2016)

  3. #13
    Quote Originally Posted by TESKATLIPOKA View Post
    pTmd
    You know we already have a dedicated steamroller section so I ask once more what's the point in creating another thread? If it's really that important to have one just for the IGP then it should have been created in the GPUs section not this one!
    The Steamroller architecture is different from the APU using Steamroller cores, isn't it? This thread is discussing a statement about APUs to have 5800 GPU level of graphics performance in 2013. So you are right that it might be posted in the wrong forum. Should we click the report button and tell the moderator, errh?

  4. #14
    Quote Originally Posted by Rottis View Post
    GPUs bandwidth usage is pretty consistent and most bandwidth goes to framebuffer access
    That's an interesting statement. Do you have any study that proves that? Not that I doubt what you say, I just find that odd
    Speaking for myself.

  5. #15
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    Quote Originally Posted by Stuckey View Post
    Sorry, so you mean Kaveri 'dual graphics' could be about the same as an HD5830 ? So that would be about the same as a GTX580m ? But presumably with the ability to seamlessly powergate the dGPU when not in use ? Thanks. I think I could probably live with that in a mid range notebook...
    Too bad it wouldn't be a "mid-range" notebook in OEM's minds.

  6. #16
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    Quote Originally Posted by 265586888 View Post
    Too bad it wouldn't be a "mid-range" notebook in OEM's minds.
    This is one of AMD's problems, I think OEMs take the piddle with pricing of AMD stuff. Look at the E350 15.6" laptops, and their relative price. I am sure AMD didn't really intend Bobcat to go up against Celeron and Pentium Duals in price and form factor

    I'd love to see "reference" AMD branded Trinity (and beyond) notbooks

    Back on topic, when will be see APUs with 150GB/s memory bandwidth?

  7. #17
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    Quote Originally Posted by laurent View Post
    That's an interesting statement. Do you have any study that proves that? Not that I doubt what you say, I just find that odd
    This thread is probably not the place for detailed break down where bandwidth usually goes.
    What I mean by 'framebuffer' is any output buffers used with rendering.
    Traditionally rendertarget textures and eventually final frame.

    I think this is very important part of the APU performance and where it will go.
    Most here are probably familiar how rendering works so I try to do simple break down to explain where memory access in rendering goes.

    Typical graphics source data flow consist of reading vertex, texture data in.
    From this input data triangles are formed, transformed to whatever target space is, rasterized and writen to target buffer(s).
    Target buffers are often large and most operation need to be read-modify-write, most often using at least two different buffers (typically color and depth, I'm not going into deferred rendering here).
    These buffers are broke into smaller areas (blocks), I'll use example 16x8 pixels as example. This holds true for both conventional and tile based.

    Simple flow would be
    1.
    - Rasterize triangle and pass each pixel overlapping target block area to shader(s)
    - Read depth-buffer block from memory
    - Read color-buffer block from memory
    2.
    - Pixel shader magic
    3.
    - Test pixel depth against depth-buffer at target location
    - if visible, write depth value to target depth block
    - if visible, write/blend to target color block
    - Write color and depth block back to memory

    There's tons of optimizations possible and done for all this, but it should be clear how bandwidth intensive this can get.

    Textures are usually taking up most memory, but are easily cached and usually packed. This is read only, mostly easily predictable load.
    Mesh topology, ie. vertex data is usually much smaller than textures.


    Here's a study about rendering memory bandwidth requirements for conventional vs. tile based rendering on mobile based 3D acceleration.
    It's not exactly current, but it gives good break down of what happens where.
    Also first hit from google: http://www.google.fi/url?sa=t&rct=j&...syIOYIe5DF9QEA
    "One solution that seems to have been reasonably effective in the past is that of public ridicule." - Alex Smith (2014, Nethack 4 about game balancing)
    "VR has been the future of gaming for the last 25 years, and will continue to be for another 25 years..." - NTMBK (2016)

  8. #18
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    Quote Originally Posted by London Dave View Post
    This is one of AMD's problems, I think OEMs take the piddle with pricing of AMD stuff. Look at the E350 15.6" laptops, and their relative price. I am sure AMD didn't really intend Bobcat to go up against Celeron and Pentium Duals in price and form factor

    I'd love to see "reference" AMD branded Trinity (and beyond) notbooks

    Back on topic, when will be see APUs with 150GB/s memory bandwidth?
    I agree. If OEM's did decide to make them as expensive as an i5/i7+decent dGPU it would be a huge opportunity lost for both the OEM's and AMD. If that happend I think AMD should seriously consider making their own.

    But back on topic too, lacking expertise in such things, could someone please explain what (if any) impact stuff like zero copy and shared memory pointers etc might have on any of the more common rendering methods ?

    In laymans terms, will it be Wow!, or meh ?

  9. #19
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    Quote Originally Posted by Stuckey View Post
    In laymans terms, will it be Wow!, or meh ?
    Wow for the sheer amount of bandwidth, the bigger is quite certainly better.

    Meh for the real performance improvements and the idea as a whole, sure 150 GB/s is nice to have, and virtually removes any "supposed" bottlenecks on the GPU. And then when you have one bottleneck removed, another part of the chip falls behind and become the new bottleneck.

    Also, giving 150 GB/s bandwidth to the APU graphics doesn't come at zero cost, power consumption, die size and manufacturability being to first items on the list for trade-offs. The last two directly affects the cost of manufacturing the APU, and the first one affects the cooling solution requirements.

    While 64-bit DDR3 at 2133 MHz has only 17.064 GB/s bandwidth, giving 150 GB/s for the APU graphics means you are giving it its own memory controller with 256-bit width and 4.5 Gbps GDDR5 memory, this figure is an aggregrate bandwidth. Quite the opposite of what AMD was promising for HSA, am I right?

  10. #20
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    I only say 150GB/s as that is roughly what the mid range HD5850 had. The 5850 I had was awesome, got it about a month before retail for ?180 and it lasted me til recently. An APU with that kind of piff for ~ ?200/$300 would clean up, at the expense of discrete GPU sales of course.

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