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Thread: ATI doesn't get enough 40nm for HD58xx

  1. #31
    >intel 4004
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    Quote Originally Posted by PY-Intel View Post
    I don't buy it
    Let me re-phrase it:
    You want to design a GPU on SOI doesn't become easier even ATI is a subsidiary of AMD. The technical stuff still exists and won't be disappear!

    And you would like a 12-month transistion from node to node? You'd think GlobalFoundries and AMD do have unlimited cash, like Intel?

  2. #32
    8-bit overflow
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    There is no need to design it. All you need is to transfer already existing design to different but nonetheless familiar (to AMD) process. This would be pretty straightforward task for AMD.

  3. #33
    OK PY-Intel, you made a statement, now explain it: why would no ASIC redesign be required.

    (I have already provided you with links which suggest just the opposite).
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  4. #34
    >intel 4004
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    Quote Originally Posted by PY-Intel View Post
    There is no need to design it. All you need is to transfer already existing design to different but nonetheless familiar (to AMD) process. This would be pretty straightforward task for AMD.
    I've heard that AMD did try with a GPU design (don't know which one), but the the conclusion is a "no go".

  5. #35
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    Quote Originally Posted by 265586888 View Post
    I've heard that AMD did try with a GPU design (don't know which one), but the the conclusion is a "no go".
    "no go" as a "can not be done" or "Not worth it when TSMC is doing so well"?

  6. #36
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    Quote Originally Posted by ShinyShoes View Post
    OK PY-Intel, you made a statement, now explain it: why would no ASIC redesign be required.

    (I have already provided you with links which suggest just the opposite).
    you changed "design" to "redesign"
    what does "redesign" mean? And why would it be required?

  7. #37
    kalizec
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    CPUs, GPUs are made up from transistors, capacitors, resistors, etc.

    There are different types of each.

    On each process node, each type is made in a different way. It's not just a 'shrink'. It is more, because a smaller transistor might signal faster, or slower. Since a lot of the stuff inside a processor comes down to things happening at the right time, this means each and every path needs to be checked and rechecked. And that is after all stuff was 'redesigned' with the new way for that process node.

  8. #38
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    nobody talks about shrink here, we are talking about the opposite here - going from 40nm TSMC to 45nm GloFo. Making slightly bigger masks how hard can it be? it would be great if GloFo had 40 nm but they don't.
    As for the SOI then anything which works on bulk will work on SOI just fine. Opposite may not be true though.

  9. #39
    Quote Originally Posted by PY-Intel View Post
    you changed "design" to "redesign"
    what does "redesign" mean? And why would it be required?
    Not sure why I am spending time justifying myself when you keep making one line statements and asking off the cuff questions without backing yourself up with evidence or rationale.

    Now this is definitely not my area of expertise so I am happy to be corrected by the many people here who actually know what they are talking about.

    An ASIC redesign would be, at a minimum, a whole new stepping or possibly a complete redesign from the ground up.

    Why? Well, to expand on Kalizec's points, SOI and bulk silicon will tend to produce circuits with different electrical characteristics, power usage, heat dissipation, frequency response, leakage, gawd knows what else I'm not aware of.

    Bottom line: the two processes do not perform the same and do not produce circuits which perform the same.
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  10. #40
    Quote Originally Posted by kalizec View Post
    CPUs, GPUs are made up from transistors, capacitors, resistors, etc.

    ...... It's not just a 'shrink'. It is more, because a smaller transistor might signal faster, or slower. Since a lot of the stuff inside a processor comes down to things happening at the right time, ........
    Any logic designer that designs circuitry that passes state information in a non-synchronisus fashion would be booted out of the industry within the first few days of his professional life.

    Every state change of every piece of logic in a CPU or GPU is passed from one functional block to the next through a gated time slot. This is the only way to control the performance of a device by a clock signal. (try halving the clock on a CPU or GPU and the performance will halve)

    No matter how much faster a new process happens to be , there should be NO requirement to redesign any of the circuitry just because active devices are switching faster.
    If the new smaller process starts producing localized hot spots on the chip, then that is another story, and may require a small layout redesign .

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