THERE HAS BEEN a lot of false information floating around about TSMC and their 40nm process. It ranged from the overly optimistic to hopelessly wrong, so lets clear the air, it is OK now.
As of early this week, the same sources that told us that the process initially had problems, then later confirmed the culprit, have told SemiAccurate that TSMC has given the technical thumbs up to their revised 40nm process. Wafers can go in any time now, in volume, with only one caveat. That caveat is that the process is good to go if you did your homework. We know ATI did, and we are pretty sure Altera did as well, but did Nvidia run enough to shake out the bugs? We will know in late September when the GT210 and GT220 are either available, or talk again turns to how one should focus on the things available now like they did at analyst day.
It should take between 10 and 12 weeks to get silicon back, so with a July 1 date for pies in the oven, a first half of September date for pies with pretty pictures on them is not unreasonable. Add a week or two for assembly, test and shipping, and you have parts.
If all goes well, we could see Juniper and Cypress at retail in September, easily beating the promised Windows Me II SP7 launch date. GT300 is currently slated for a mid-July tapeout, but unless the stars align, no less than 16 mid-level miracles occur, and most of the luck in Silicon Valley converges on NV HQ, you won’t see it this year.
That brings us to the next topic, the quality of information going around, and the so called ‘analysts’. I used to have a very dim view on the species, but then I looked a bit deeper and discover there were two sub-species. These are the technically aware Analysus financii technicus and the terminally clueless Analysus financii dinnerguestus. Sadly, the gene that differentiates those sub-species are closely linked to those that control loudness and promiscuity.
The clueless species had a classic showing last week shortly after TSMC gave the all-clear to partners, and that was reprinted all over the net, particularly in some more technically reputable journals. It was taken from a dubious source to begin with and then not credited by the analyst. The short story is that some claim yields are still below 30% on the TSMC 40nm process.
If you have even the vaguest clue as to how semiconductors are made, you will know that a process does not have yield, and it never will. It is like someone stating the frequency of Intel semiconductors as a whole, it makes no sense. Yield is process AND chip dependent. Things like leakage, defect density, and what any given IC’s targets are all determine yield, not some magical property of the process.
For any given process, you can design an IC that has anywhere between 0% and 100% yield. Claiming that a process has a yield of X is akin to standing on a hill shouting “I am ignorant” to anyone who will listen. No volume part that SemiAccurate is aware of has ever run as low as 30% yields on the TSMC 40nm process, period.
In the end, the take home message is that the TSMC 40nm process is now just peachy now if you did your homework, and initial wafers are either in, or will be, in days. You should see chips with lower layer counts on the market in early September, followed by more complex parts a few weeks later. Things are finally back on track.S|A
Latest posts by Charlie Demerjian (see all)
- AMD talks Threadripper, Ryzen Mobile, and Ryzen Pro - May 22, 2017
- AMD calls Naples Epyc during Analyst Day - May 17, 2017
- Intel’s new Scalable Xeon branding is just a price increase - May 5, 2017
- Are consumer PCs safe from the Intel ME/AMT exploit? - May 3, 2017
- Remote security exploit in all 2008+ Intel platforms - May 1, 2017