GLOBAL FOUNDRIES HAD the second keynote at the Common Platform alliance conference Tuesday, the topic was manufacturing. Chia Song Hwee, COO of Global Foundries went into more details about what the alliance is doing to make chips, and how they were planning to work together for the benefit of their customers.
First up was a brief rundown of some of the challenges in manufacturing the chips of the future, this is the second step after the basic research is completed. While related to questions about ‘what process’, volume manufacturing technology is centered around how you do something in large quantities, and that is arguably harder than the basic science.
Making a piece of silicon that has a single transistor with features measured in nm is tough, making a chip with a billion of them on it is much harder. Making a wafer with hundreds of those chips on each one, at volumes in the thousands of wafers a day, is even more challenging, not to mention expensive. Lets just say that once you know what recipe you want to cook, you are far from done.
Some of the challenges that are in the past for the Common Alliance, basically the technologies, are in production now. Things like copper integration and immersion are examples of these, if you think drawing a billion transistors on a chip is hard, try and do it under water. Near term problems that are basically solved are high-K/metal gate (HKMG) and some packaging problems. On the hit list now are FinFETs, more complex 3D packaging, 450mm wafers, and how to keep scaling going. In hindsight, past ‘really hard’ problems look easy from where some are standing today.
Once again cost is a huge driver here. Expanding on Mr Woo’s keynote, Mr Hwee went into a little more depth on the costs involved in making cutting edge chips. Global Foundries says the cost of developing a process, not including the long term R&D, is in the $1-2 Billion range, about where Samsung said it was. That is only the start though.
From there, a company will need to spend more than $250 million on design enablement, a fancy name for making the tools to design chips with. This includes a lot of software, lots of licensed IP up to and including full ARM cores, and tons of testing and validation work. Before a customer is going to commit tens of millions of dollars to a project, they usually want some proof that if they do their part, the foundry’s bits will work as promised.
Then there is the little problem of building the fab itself, estimated at $5-7 Billion for a current 300mm node, more in the future. Most foundries don’t have only one fab either, so the spending is likely a multiple of this paltry sum. Now you are starting to see why semiconductors are considered a capital intensive endeavor.
Customers have it easy though, or at least easier than the foundries. The estimates given for designing a chip on the 28nm node are in the $40-50 million range, but that budget is easy enough to balloon if you have even a minor little slip. This number isn’t counting software development, something that will add an estimated $50 million or so to the tab.
The foundry side costs are being mitigated somewhat by the Common Platform alliance, but customers are somewhat on their own. This is why the number of tapeouts on each new node tends to drop dramatically, which is not good if you are a CFO wondering if you should spend the better part of $10 billion to bother with developing the next node.
One reason that the Common Platform companies are taking the risk is cell phones, specifically smartphones. Currently they are about 1/4 of the phone market, and depending on who you believe, will hit half or more by mid-decade, with typical prognostication margins of error.
Those same pundits all take the easy road and say that video will be the overwhelmingly dominant part of IP traffic in the coming years, and that also balloons a device’s silicon needs. As far as the fab guys are concerned, smart phones, and the related infrastructure they bring are the future. Lets be honest and say that it isn’t exactly a tough call by the analysts, and for the foundry CFOs, it is a pretty safe bet.
One way to help the customers, and potentially lower the cost of making a new chip is to set standards, and that is one thing the Common Platform guys are aiming to do according to Mr. Hwee. The idea is to have compatibility across the various processes that each vendor offers so a customer can shop around, dual or triple source, and generally not be chained to a single foundry.
While this may sound egalitarian, it is contrary to the desires of the foundries in many respects. SemiAccurate hears that at least one big customer is demanding second sourcing, and other are likely doing so in the background, it is in the customer’s best interest. Compatibility has become a ‘must do’ issue for the foundries in recent months, so they are.
Compatible is one of those words that most customers think means something while most vendors think it means something completely different. Take Microsoft Office and their OOXML ‘spec’. It was submitted to ECMA and ‘standardized’ as ECMA-376. MS Office’s OOXML ‘standard’ isn’t actually compatible with ECMA-376 though, leading to lots of hilarity for those working out bugs and trying to work with the ‘standard’. Since this mess means that only MS products work with MS products correctly, the impetus for the company to change their antisocial behavior is somewhat lacking.
Foundries could do the same thing, call things compatible while hamstringing them in every way, but the Common Platform companies appear to not be doing that. That said, what do they mean by compatible? On the lowest level, it means GDS II compatibility, essentially a file format so you can take your tapeout info to any fab you want and have them read it without error prone translation problems.
Common Platform is going beyond that, quite a bit beyond. All of the three big partners, and ST Micro too, are doing something called FabSynch at 28nm. Basically this means the four bring up their fabs together, and promise electrical equivalence on the products being manufactured.
If the process itself is a black box to the customer, this combined with GDS II compatibility means what they give the foundry is the same, and what they get out is the same. The middle is mostly irrelevant as long as it does what was promised. That is a pretty good definition of compatible, but as always, lets see if practice matches the talk.
To make this happen, the partners have promised to share yield and reliability information on an ongoing basis, and basically work together to make sure things stay working. If all four continue to talk to each other, this should be much more meaningful than it sounds. Group hugs for all.
During a press Q&A session, Mr Hwee was asked if that meant you could move masks from one fab to another, and the answer was no. Things aren’t quite there yet, and with each shrink, that becomes harder to do, so it may never come about. That said, the number of customers splitting a single product between multiple foundries is effectively zero now, so it isn’t a big concern.
When asked if the idea of splitting a line between two foundries was being encouraged, that answer was yes. The cost of making a mask set for the 32/28nm node is in the millions, so you would need to run an awful lot of wafers to have this make economic sense though. It will be very useful for running multiple similar products in a line, GPUs are a good example.
One way of validating this whole concept is to work together on test chips. Right now, the Common Platform fabs do have jointly developed test chips, and are working together to make more. The idea is that any customer can look at similar results from each fab and compare and contrast. If all goes well, there should be no differences of note.
In the end, Global Foundries did a good job of outlining what the different companies are doing to work with each other, and why that is important. The goal is to minimize cost while giving peace of mind to the customers. So far, it looks like they are doing just that.S|A
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