In the last part of the Intel (NASDAQ:INTC) phone/Medfield article, we looked at the package and the core, now it is time for the good stuff. The magic of this chip is the rest of the SoC called Penwell, not the core itself.
As a brief recap, there are three names you should know about, Saltwell, Penwell, and Medfield. Saltwell is the 3rd generation Atom core, built on a 32nm-LP process, and is essentially a tweaked Lincroft/Moorestown core. Medfield is the CPU family that comprises all 3rd generation 32nm Atom cored products, at least until marketing sneezes. Penwell is the full SoC that incorporates Saltwell and the rest of the parts that are on the silicon. It is the focus of this part of the story, and it looks like this.
Penwell block diagram
Above is the basic block diagram for the SoC, and it isn’t much more than a list of bullet points. There were much more detailed versions shown in SemiAccurate’s briefing, but not provided, so we will supplement the above as best we can. There will be some omissions, and possibly a few errors, so apologies in advance, it is the best we were provided.
In the CPU block, we have have the Saltwell core described in the first part. It has one core, two threads, and runs at a maximum of 1600MHz in turbo mode. The L1 caches are also here, but not the 512K L2 cache. Both of these units, and for that matter almost every block here is likely replaceable on a whim.
Intel showed some awe inspiring slides with Medfield described as a Single Core on a blue arrow. Next to it was a chip labelled Dual Core Dual Graphics, and next to that Multi Core. Confusingly, both are code named, “Future”, something sure to cause confusion at Intel. The take home message is that this is a modular family, and expect variants on 32nm before the 22nm Silvermont based chips come out. Some may not be code named “Future” though.
On the memory side, there is a box labelled LP-DDR2 Controller, and the closely associated I/O block to it’s right. The LP-DDR2 controller is just that, and it supports up to two 32-bit LP-DDR2 channels at up to 800MHz. Unfortunately, each channel only supports up to 512MB, or 1GB max memory for the entire SoC. This looks like it could severely limit the prospects of the part, and it is likely why we will never see 64-bit Medfields.
Curiously, the controller itself was said to be a carry over from the older parts while the I/O block was listed as all new on Penwell. This probably isn’t listed because of the process change, if it was, nothing would be carried over. It is either support for new types of physical layers or higher speeds, but we can’t say for sure. The end result is probably a bit less power used and higher performance.
The next big set of functionality is the video displays, but not the cameras. These blocks, 2D/3D graphics, Video Decode, Video Encode, and Display Controller are all closely linked. All but the controller are Imagination Technology IP based, great hardware that somehow never works right when Intel provides the software. Luckily, this time is said to be different. Again. More on this later, for now, lets stick to the hardware itself, something that is quite good.
The 2D/3D graphics block is a fairly standard Imagination SGX 540 GPU running at 400MHz. The older Atoms had an SGX 535 in them, the 540 has twice the SIMDs of the smaller variant, so expect more horsepower this time around. This is the same GPU architecture found in the Apple A5, TI OMAP4, several Samsung chips, and close to the Playstation Vita GPU. The MP family in the Vita is similar to the one that will be incorporated in the dual core dual graphics chip code named “Future” coming in the future. Blue arrows don’t lie.
Intel lists the GPU as supporting OpenGL ES2.0, OpenVG, and DX9, but the Imagination spec sheet lists the device as being capable of DX10.1 too, Intel does not. This would normally be a dismiss-able footnote, but given Intel’s abject failure to get Cedar Trail to work at all, it is more than academic. If you don’t recall, Cedar Trail is the desktop variant of Penwell with an SGX 545 GPU. Both the 540 and 545 have no problems in non-Intel guise, so this is a very good hardware choice for the company. Happy thoughts.
Imagination also powers the video encode and decode, with a VDX 385 block under the Video Decode sticker, and a VDX 285 lurking beneath the Video Encode covers. Both are capable of supporting 1080p30 formats, although that may be complicated by the image processor and I/O capabilities. In any case, the Display Controller block has been updated, there are now three controller pipes to select from.
Moving back to the I/O block on the right, this is where it all the video goes in and out. Duh. Penwell has three interfaces, two MIPI-DSI that share four lanes (4-0/3-1/2-2) for internal screens, and an HDMI 1.3a controller for external panels. The maximum panel size available for Internal screens is 1366 * 786, but the HDMI can output 1920 * 1080 at 30FPS, possibly more.
Interestingly enough, all of the video components are listed at 1080p30 for maximums, but can likely go much higher. This is most likely a thermal/TDP limit, not any silicon handcuffs. If you were to add a bigger battery and heatsink, we have no doubt that those limits would vanish. 1080p60 was referenced here and there by Intel, so a little more juice would go a long way here.
Although it may seem related, the block labelled Image Signal Processor is not, it isn’t even close. This particular block is by Intel, or the company Intel recently bought, Silicon Hive. They made image processors like this one, and are not related to any of the Imagination cores above. All this does is take raw camera data at up to 240MPPS for video, 16MP for stills, and tweak it. Things like image stabilization, color adjustment, and various clean up effects are available, and more can be programmed at will.
If you don’t want to do the math, this block can easily chew through 1080p30 input from the camera, clean it up, and then hand it off to the VDX 285 for encoding. This data comes in across two MIPI-CSI ports, one four lane and one single lane, basically two cameras capable of still or video output.
The last bit under the Image Signal Processor block that isn’t broken out on the diagram is memory. Penwell has 256KB of SRAM for things like the image processor to use. This may not seem like much, but it enables the chip to pull off burst mode, and not cause visible glitches if something gets blocked or interrupted here and there. This is the same scratch space as the last two generations of Atoms had, but this time, it looks like Intel has the horsepower to use it well now.
That memory is also used by the block called Security Programmable Execution Engine Environment and Crypto Engine. Intel isn’t saying much about this block for obvious reasons, but given the number of McAfee labels all over the presentations, you know what it is going to be sold as. In any case, a secure on-chip scratch space for crypto is never a bad thing, for more than just performance reasons.
Intel is saying the IOSF-OCP Bridge is all new, but not much else about the block. There is a new JTAG/cJTAG port listed, but the rest of the plumbing is a carry over from older variants. For debugging, this is supported by a MIPI-PTI/DFX interface as well as the older POSI/EYOS signalling (Puff Of Smoke Interface/Engineers Yelling “Oh Darn”). We think most will stick with JTAG now that it is an option.
The last part is the left side I/O block, and the majority of this is carried over from older Atoms. Other than pretty standard I/O blocks that need to be re-worked for the 32nm-LP process, there isn’t much to add. The majority of the new bits were added to support the new chipset called Avatele Passage, and a new Intel/Infineon radio.
Avatele Passage, the chip, not the unpleasant medical procedure, is supported by a ULPI interface for better USB implementation. There is a UART now, and various tweaks to other blocks. All of the voltage regulation, audio support, and some display support, is handled under local anaesthetic by Avatele Passage.
The other outpatient, err, associated chip, is the Intel/Infineon XMM 6260 modem that supports HSPDA+. This communicates via a new MIPI HSI interface in the I/O block, and talks to the various other radios and support chips. Mobile TV, FM, Wi-FI, and near field communications are listed, but others can be added. Penwell has a UART now to better support the extra chips.
All of the above is what makes Penwell a SoC rather than a CPU. Other than the last two support chips, it really is a complete system on a chip. If you count the stacked DRAMs explained in the previous article, it is a nearly complete system on a package. All of the things that matter to the user are comprehensively updated, improved, and made more efficient. The few options that Moorestown offered have been narrowed to basically none, but that isn’t necessarily a bad thing, especially for power use.
The hardware of Penwell looks damn good, as did the hardware of Moorestown before it. Technically speaking, both parts check all the right boxes, and include just about everything you need for a complete system. Some things may not have the headroom, some may not be exactly what you need, but you can say that about any SoC out there. Luckily, as far as serious technical flaws go, we can’t see any.
So Penwell is perfect, and is going to take over the world, right? In an unusual twist, even Intel doesn’t claim that this time around. That is both the biggest change from the previous generation, and the reason that we see some hope for the company in phones. Motorola and Lenovo are on board, and others are guaranteed to follow in short order. But will it succeed in the market once the spotlight moves to the next shiny thing? That is the focus of the next part of the story, software, devices, and the market.S|A
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