SuVolta shrinks the transistor variations

Advanced PowerShrink platform significantly reduced transistor variations.

SuVolta logo 63x17 SuVolta shrinks the transistor variations

As dimensions keep shrinking so does the efficiency of traditional transistors.  There are a couple of different solutions to this particular problem.  Intel has gone the way of FinFET’s or “3D transistors” as Intel has named the transistors. The 3D nomenclature should not be confused with die stacking which is also referred to as 2.5D or 3D by other companies.

With the 3D transistor the transistor itself is raised from the substrate thereby eliminating much of the leakage, but also requiring special manufacturing.  Another option, which is pursued by the startup SuVolta, is a method to reduce the transistor variation across a die.

Variation in transistors means that that the Vt, or threshold voltage, differs slightly between the individual transistors on a die. The variations are very small, but significant enough to waste power.

Therefore SuVolta has introduced the PowerShrink low-power CMOS platform, based on earlier technologies, using a Deeply Depleted Channel (DDC) transistor, that significantly lowers power consumption without sacrificing performance across a wide range of integrated circuit (IC) products, including the processors, SRAMs, and SOCs that are critical to today’s mobile systems, according to the description provided by SuVolta. SuVolta’s technology lowers both active power and leakage power consumption by decreasing threshold voltage (VT) variation by 50%. This reduced VT variation enables up to 30% scaling of power supply voltage (VDD) while maintaining performance, and eliminates the worst-case tail of the transistor VT distribution that causes the majority of IC product leakage power consumption.  Most notably SuVolta estimates that leakage power can be reduced by 80% or more.

According to SuVolta the DDC transistor enables 30% scaling of supply voltage (VDD) while maintaining performance, and eliminates the worst-case tail of the transistor VT distribution that causes the majority of IC product leakage, by decreasing threshold voltage, VT, variation by 50% variation, VDD scaling, and leakage power reduction

The DDC transistor increases drive current (IEFF) by 10% or more by increasing channel mobility by 30% or more

IEFF and mobility increases relative to conventional technology at equivalent voltage are even greater when VDD is scaled more than 30%.

But most importantly SuVolta’s Deeply Depleted Channel™ (DDC) transistor leverages existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials. SuVolta’s PowerShrink platform also uses conventional design tools and design flows.S|A

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